SNLS739 October   2023 DS320PR410

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNQ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss 50 MHz to 1.25 GHz -24 dB
1.25 GHz to 2.5 GHz -19 dB
2.5 GHz to 4.0 GHz -18 dB
4.0 GHz to 8.0 GHz -15 dB
8.0 GHz to 16 GHz -9 dB
RLRX-CM Input common-mode return loss 50 MHz to 2.5 GHz -17 dB
2.5 GHz to 8.0 GHz -13 dB
8.0 GHz to 16 GHz -8 dB
XTRX Receiver-side pair-to-pair isolation; Port A or Port B Minimum over 10 MHz to 16 GHz range -50 dB
Transmitter
VTX-AC-CM-PP Tx AC peak-to-peak common mode voltage Measured with lowest EQ, GAIN = L4; PRBS-7, 32 Gbps, over at least 106 bits using a bandpass-Pass Filter from 30 Khz - 500 Mhz 50 mVpp
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute delta of DC common mode voltage during L0 and electrical idle VTX-CM-DC = |VOUTn+ + VOUTn–|/2, measured by taking the absolute difference of VTX-CM-DC during PCIe state L0 and Electrical Idle 0 120 mV
VTX-RCV-DETECT Amount of voltage change allowed during receiver detection Measured while Tx is sensing whether a low-impedance receiver is present. No load is connected to the driver output 0 600 mV
RLTX-DIFF Output differential return loss 50 MHz to 1.25 GHz -24 dB
1.25 GHz to 2.5 GHz -21 dB
2.5 GHz to 4.0 GHz -19 dB
4.0 GHz to 8.0 GHz -16 dB
8.0 Ghz to 16 Ghz -14 dB
RLTX-CM Output common-mode return loss 50 MHz to 2.5 GHz -15 dB
2.5 GHz to 8.0 GHz  -12 dB
8.0 GHz to 16 GHz -11 dB
XTTX Transmit-side pair-to-pair isolation Minimum over 10 MHz to 16 GHz range -50 dB
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either low-to-high or high-to-low transition.  100 130 ps
LTX-SKEW Lane-to-lane output skew Between any two lanes within a single transmitter.  20 ps
TRJ-DATA Additive random jitter with data Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. 45 fs
TRJ-INTRINSIC Intrinsic additive random jitter with clock  Jitter through redriver minus the calibration trace. 16 Ghz CK. 800 mVpp-diff input swing. 35 fs
JITTERTOTAL-DATA Additive total jitter with data Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. 1.2 ps
JITTERTOTAL-INTRINSIC Intrinsic additive total jitter with clock Jitter through redriver minus the calibration trace. 16 Ghz CK. 800 mVpp-diff input swing. 0.3 ps
FLAT-GAIN Broadband DC and AC flat gain - input to output,  measured at DC Minimum EQ, GAIN = L0  -5.6 dB
Minimum EQ, GAIN = L1  -3.8 dB
Minimum EQ, GAIN = L2  -1.2 dB
Minimum EQ, GAIN = L3  2.6 dB
Minimum EQ, GAIN = L4 (Float)  0.6 dB
EQ-MAX16G EQ boost at max setting (EQ INDEX = 19) AC gain at 16 GHz relative to gain at 100 MHz.  23 dB
FLAT-GAINVAR Flat gain variation across PVT measured at DC GAIN = L4, minimum EQ setting. Max-Min.  -2.5 1.5 dB
EQ-GAINVAR EQ boost variation across PVT At 16 Ghz. GAIN = L4, maximum EQ setting. Max-Min.  -3.0 4.0 dB
LINEARITY-DC Output DC linearity at GAIN = L4 1800 mVpp
LINEARITY-AC Output AC linearity at 16 Gbps, with GAIN = L4 1100 mVpp
at 32 Gbps, with GAIN = L4 850 mVpp