SNLS709B december   2021  – june 2023 DS560DF810

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Description (continued)
  7. 6Device and Documentation Support
    1. 6.1 Documentation Support
      1. 6.1.1 Related Documentation
    2. 6.2 Receiving Notification of Documentation Updates
    3. 6.3 Support Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  8. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • -channel multi-protocol retimer with integrated signal conditioning
  • All channels lock independently to both PAM4 and NRZ data rates from 19.6 to 28.9 GBd (including div-by-2 and div-by-4 sub-rates)
  • Suitable for up to CEI-56G, Ethernet™ (400 GbE), fibre channel (64GFC), InfiniBand™ (HDR), and CPRI/eCPRI PCB, copper cable, and optical applications
  • Automatic lane rate switching for CDR lock up to five different combinations of baud rates and modulation types
  • Low latency: <2000 ps (typical) at 26.5625 GBd
  • Continuously adaptive time linear equalizer (CTLE), RX feed-forward equalizer (FFE), and decision feedback equalizer (DFE) to support 30+ dB channel loss at 13.28 GHz
  • Integrated 2×2 crosspoint
  • Adjustable 4-tap TX FFE filter
  • Gearbox mode support (NRZ/PAM4 bit mux/de-mux, NRZ/PAM4 serializer/deserializer)
  • On-chip eye opening monitor (EOM), PRBS generator, and PRBS checker for debug
  • Dual 1.8-V and 1.2-V supplies
  • –40°C to +85°C operating temperature range
  • 8.00 mm × 13.00 mm BGA package with integrated AC coupling capacitors