7.3.1 4-Level Input Configuration Guidelines

The 4-level input pins use a resistor divider to help set the four valid levels. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Using the 1-kΩ pullup, 1-kΩ pulldown, no connect, or 20-kΩ pulldown provide the optimal voltage levels for each of the four input states.

Typical 4-level input thresholds:

• Level 1 to 2 = 0.2 V_IN or V_DD
• Level 2 to 3 = 0.5 V_IN or V_DD
• Level 3 to 4 = 0.8 V_IN or V_DD

To minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and pulldown resistors are recommended. If several 4-level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example; combining two inputs with a single 500-Ω resistor is a good way to save board space. For the 20 kΩ to GND, this should also scale to 10 kΩ.

7.4.1 Pin Control Mode

When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically adjusted per the De- Emphasis table below. The RXDET pins provides automatic and manual control for input termination (50 Ω or > 50 kΩ). RATE setting is also pin controllable with pin selections (Gen 1/2, auto detect and Gen 3). The receiver electrical idle detect threshold is also adjustable through the SD_TH pin.

7.4.2 SMBUS Mode

When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (RATE, RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and when ENSMB is driven low all registers are reset to their default state. If PRSNT is asserted while ENSMB is high, the registers retain their current state.

Equalization settings accessible through the pin controls were chosen to meet the needs of most PCIe applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the SMBus registers. Each input has a total of 256 possible equalization settings. The 4-Level Input Configuration Guidelines show the 16 setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-emphasis levels are set by registers.

7.5.1 System Management Bus (SMBus) and Configuration Registers

The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ to VDD to enable SMBus slave mode and allow access to the configuration registers.

The DS80PCI102 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS80PCI102 has a 7-bit slave address. The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the AD[3:0] inputs. Below are the 16 addresses.

The SDA/SCL pins are 3.3-V tolerant, but are not 5-V tolerant. An external pullup resistor is required on the SDA and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.

7.5.2 Transfer of Data Through the SMBus

During normal operation the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A high-to-low transition on SDA while SCL is High indicates a message START condition.

STOP: A low-to-high transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for t_HIGH then the bus will transfer to the IDLE state.

7.5.3 SMBus Transactions

The device supports WRITE and READ transactions. See Table 10 for register address, type (Read/Write, Read Only), default value and function information.

7.5.4 Writing a Register

To write a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
2. The Device (Slave) drives the ACK bit (0).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (0).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (0).
7. The Host drives a STOP condition.

The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.

7.5.5 Reading a Register

To read a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
2. The Device (Slave) drives the ACK bit (0).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (0).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a 1 indicating a READ.
7. The Device drives an ACK bit 0.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit 1 indicating end of the READ transfer.
10. The Host drives a STOP condition.

The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.

See Table 10 for more information.

Figure 7. Typical SMBus Write Operation

7.5.6 EEPROM Programming

The DS80PCI102 supports reading directly from an external EEPROM device by implementing SMBus Master mode. When using the SMBus master mode, the DS80PCI102 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the following guidelines should be followed:

• Set the DS80PCI102 into SMBus Master Mode.
  • ENSMB (PIN 3) = Float
• The external EEPROM device must support 1-MHz operation.
• The external EEPROM device address byte must be 0xA0.
• Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.
• The device address can be set with the use of the AD[3:0] input up to 16 different addresses. Use the example below to set each of the SMBus addresses.
  • AD[3:0] = 0001'b, the device address byte is 0xB2
  • AD[3:0] = 0010'b, the device address byte is 0xB4
  • AD[3:0] = 0011'b, the device address byte is 0xB6
  • AD[3:0] = 0100'b, the device address byte is 0xB8
• The master implementation in the DS80PCI102 supports multiple devices reading from one EEPROM. When tying multiple devices to the SDA and SCL pins, use these guidelines:
  • Use adjacent SMBus addresses for the 4 devices
  • Use a pullup resistor on SDA; value = 4.7 kΩ
  • Use a pullup resistor on SCL; value = 4.7 kΩ
  • Daisy-chain READEN (Pin 17) and DONE (Pin18) from one device to the next device in the sequence.
    1. Tie READEN of the first device in the chain (U1) to GND
    2. Tie DONE of U1 to READEN of U2
    3. Tie DONE of U2 to READEN of U3
    4. Tie DONE of U3 to READEN of U4
    5. Optional: Tie DONE of U4 to a LED to show each of the devices have been loaded successfully

7.5.6.1 Master EEPROM Programming

The following example represents a 2 kbits (256 × 8-bit) EEPROM in hex format for the DS80PCI102 device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the same SMBus line. There is a CRC enable flag to enable or disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the MAP bit is not present, the configuration data start address immediately follows the 3-byte base header. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are 37 bytes of data size for each DS80PCI102 device. For more details about EEPROM programming and Master mode, refer to SNLA228.

Figure 8. Typical EEPROM Data Set

NOTE

The maximum EEPROM size supported is 8kbits (1024 × 8 bits).

The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the DS80PCI102, or 40 bytes in total. The result of this calculation is placed immediately after the DS80PCI102 data in the EEPROM, which ends with "5454". The CRC-8 in the DS80PCI102 uses a polynomial = x⁸ + x² + x + 1.

There are two pins that provide unique functions in SMBus Master mode:

• DONE
• READEN

When the DS80PCI102 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the READEN pin goes low. When the DS80PCI102 is finished reading its configuration from the external EEPROM, it drives the DONE pin low. In applications where there is more than one DS80PCI102 on the same SMBus, bus contention can result if more than one DS80PCI102 tries to take control of the SMBus at the same time. The READEN and DONE pins prevent this bus contention. The system should be designed so that the READEN pin from one DS80PCI102 in the system is driven low on power-up. This DS80PCI102 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will drive the DONE pin low. This pin should be connected to the READEN pin of another DS80PCI102. When this second DS80PCI102 senses its READEN pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE pin low. By connecting the DONE pin of each DS80PCI102 to the READEN pin of the next DS80PCI102, each DS80PCI102 can read its initial configuration from the EEPROM without causing bus contention.

Figure 9. Typical Multi-Device EEPROM Connection Diagram

Table 7. Single Device with Default Value

Table 8. Multi-Device EEPROM Register Map Overview^(1)(2)(3)(4)

Table 9. Multi DS80PCI102 EEPROM Data

Table 10. SMBus Register Map