SNLS324F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 3.3-V or 2.5-V Supply Mode Operation

The DS80PCI402 has an optional internal voltage regulator to provide the 2.5-V supply to the device. In 3.3-V mode, the VIN pin = 3.3 V is used to supply power to the device and the VDD pins should be left open. The internal regulator will provide the 2.5 V to the VDD pins of the device and a 0.1-µF capacitor is needed at each of the five VDD pins for power supply de-coupling (total capacitance should be ≤ 0.5 µF), and the VDD pins should be left open. The VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5-V mode, the VIN pin should be left open and 2.5 V supply must be applied to the VDD pins. The VDD_SEL pin must be left open (no connect) to disable the internal regulator.

The DS80PCI402 can be configured for 2.5-V operation or 3.3-V operation. The lists below outline required connections for each supply selection.

3.3-V Mode of Operation

  1. Tie VDD_SEL = 0 with 1-kΩ resistor to GND.
  2. Feed 3.3-V supply into VIN pin. Local 1.0 µF decoupling at VIN is recommended.
  3. See information on VDD bypass below.
  4. SDA and SCL pins should connect pullup resistor to VIN
  5. Any 4-Level input which requires a connection to "Logic 1" should use a 1-kΩ resistor to VIN

    2.5-V Mode of Operation

  6. VDD_SEL = Float
  7. VIN = Float
  8. Feed 2.5-V supply into VDD pins.
  9. See information on VDD bypass below.
  10. SDA and SCL pins connect pullup resistor to VDD for 2.5 V uC SMBus IO
  11. SDA and SCL pins connect pullup resistor to VDD for 3.3 V uC SMBus IO
  12. Any 4-Level input which requires a connection to "Logic 1" should use a 1-kΩ resistor to VIN
GUID-D7C2D551-F046-4539-ACEA-667335DD61CD-low.gifFigure 10-1 3.3 V or 2.5 V Supply Connection Diagram