SNLS324F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.5 SMBus Controller Mode

The DS80PCI402 device supports reading directly from an external EEPROM device by implementing SMBus Controller Mode. When using the SMBus Controller Mode, the DS80PCI402 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific guidelines.

  • Set ENSMB = Float — enable the SMBus Controller Mode.
  • The external EEPROM device address byte must be 0xA0 and capable of 1-MHz operation at 2.5-V and 3.3-V supply. The maximum allowed size is 8 kbits (1024 bytes)
  • Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.

When tying multiple DS80PCI402 devices to the SDA and SCL bus, use these guidelines to configure the devices.

  • Use SMBus AD[3:0] address bits so that each device can loaded its configuration from the EEPROM. Example below is for 4 devices.
    • U1: AD[3:0] = 0000 = 0xB0
    • U2: AD[3:0] = 0001 = 0xB2
    • U3: AD[3:0] = 0010 = 0xB4
    • U4: AD[3:0] = 0011 = 0xB6
  • Use a pullup resistor on SDA and SCL; value = 2 kΩ
  • Daisy-chain READ_EN (pin 26) and ALL_DONE (pin 27) from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time.
    1. Tie READ_EN of the first device in the chain (U1) to GND
    2. Tie ALL_DONE of U1 to READ_EN of U2
    3. Tie ALL_DONE of U2 to READ_EN of U3
    4. Tie ALL_DONE of U3 to READ_EN of U4
    5. Optional: Tie ALL_DONE output of U4 to a LED to show the devices have been loaded successfully

The following example represents a 2 kbits (256 × 8-bit) EEPROM in hex format for the DS80PCI402 device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the SMBus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed pattern (0xA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS80PCI402 address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are 37 bytes of data size for each DS80PCI402 device.

:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8

:200020008005F5A800005454000000000000000000000000000000000000000000000000F6

:20006000000000000000000000000000000000000000000000000000000000000000000080

:20008000000000000000000000000000000000000000000000000000000000000000000060

:2000A000000000000000000000000000000000000000000000000000000000000000000040

:2000C000000000000000000000000000000000000000000000000000000000000000000020

:2000E000000000000000000000000000000000000000000000000000000000000000000000

:200040000000000000000000000000000000000000000000000000000000000000000000A0

For more information in regards to EEPROM programming and the hex format, see SNLA228.