SNLS209M November   2005  – January 2017 DS90C124 , DS90C241

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements - Serializer
    7. 6.7 Switching Characteristics - Serializer
    8. 6.8 Switching Characteristics - Deserializer
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Initialization and Locking Mechanism
      2. 8.3.2 Data Transfer
      3. 8.3.3 Resynchronization
      4. 8.3.4 Pre-Emphasis
      5. 8.3.5 AC-Coupling and Termination
        1. 8.3.5.1 Receiver Termination Options
          1. 8.3.5.1.1 Option 1
            1. 8.3.5.1.1.1 Option 2
            2. 8.3.5.1.1.2 Option 3
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down
      2. 8.4.2 Tri-State
      3. 8.4.3 Progressive Turn-On (PTO)
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using the DS90C241 and DS90C124
      2. 9.1.2 Display Application
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Noise Margin
        2. 9.2.2.2 Transmission Media
        3. 9.2.2.3 Live Link Insertion
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
  • User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
  • Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP and THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS Inputs and Control Pins Have Internal Pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Temperature Range: –40°C to 105°C
  • Greater Than 8-kV HBM ESD Tolerant
  • Meets AEC-Q100 Compliance
  • Power Supply Range: 3.3 V ± 10%
  • 48-Pin TQFP Package

2 Applications

  • Automotive Central Information Displays
  • Automotive Instrument Cluster Displays
  • Automotive Heads-Up Displays
  • Remote Camera-Based Driver Assistance Systems

3 Description

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.

The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90C124
DS90C241		 TQFP (48) 7.00 mm x 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

DS90C124 DS90C241 20171901.gif

4 Revision History

Changes from L Revision (April 2013) to M Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Deleted Lead temperature, soldering (260°C maximum) from Absolute Maximum RatingsGo
  • Added Thermal Information tableGo
  • Added Typical Characteristics (PCLK = 5 MHz and PCLK = 25 MHz plus pre-emphasis)Go

Changes from K Revision (April 2013) to L Revision

  • Changed layout of National Semiconductor Data Sheet to TI formatGo