8.3.1 Initialization and Locking Mechanism

Initialization of the DS90C241 and DS90C124 must be established before each device sends or receives data. Initialization refers to synchronizing the PLLS of the serializer and the deserializer together. After the serializers locks to the input clock source, the deserializer synchronizes to the serializers as the second and final initialization step.

1. When V_CC is applied to both serializer or deserializer, the respective outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When V_CC reaches V_CC OK (2.2 V) the PLL in serializer begins locking to a clock input. For the serializer, the local clock is the transmit clock, TCLK. The serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the serializer block is now ready to send data patterns. The deserializer output remains in TRI-STATE while its PLL locks to the embedded clock information in serial data stream. Also, the deserializer LOCK output remains low until its PLL locks to incoming data and sync-pattern on the RIN± pins.
2. The deserializer PLL acquires lock to a data stream without requiring the serializer to send special patterns. The serializer that is generating the stream to the deserializer automatically sends random (non-repetitive) data patterns during this step of the Initialization State. The deserializer locks onto the embedded clock within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded input bit stream. In order for the deserializer to lock to a random data stream from the serializer, it performs a series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this locking procedure is independent on the data pattern, total random locking duration may vary. At the point when the CDR of the deserializer locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The deserializer’s LOCK pin is a convenient way to ensure data integrity is achieved on receiver side.

8.3.2 Data Transfer

After serializer lock is established, the inputs DIN0 to DIN23 may be used to input data to the serializer. Data is clocked into the serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable through the TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The serializer outputs (DOUT±) are intended to drive point-to-point connections as shown in Figure 19.

CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream. The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any precoding of data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically performed within serializer and deserializer.

Serialized data and clock or control bits (24 +4 bits) are transmitted from the serial data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is 35 MHz, the serial rate is 35 × 28 = 980 Mega bits per second. Because only 24 bits are from input data, the serial payload rate is 24 times the TCLK frequency. For example, if TCLK = 35 MHz, the payload data rate is 35 × 24 = 840 Mbps. TCLK is provided by the data source and must be in the range of 5 MHz to 35 MHz nominal. The serializer outputs (DOUT±) can drive a point-to-point connection. The outputs transmit data when the enable pin (DEN) is high, TPWDNB is high. The DEN pin may be used to TRI-STATE the outputs when driven low.

When the deserializer channel attains lock to the input from a serializer, it drives its LOCK pin high and synchronously delivers valid data and recovered clock on the output. The deserializer locks onto the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high, data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the RRFB input. ROUT[23:0], LOCK, and RCLK outputs each drive a maximum of 8-pF load with 35-MHz clock. REN controls TRI-STATE for ROUTn and the RCLK pin on the deserializer.

8.3.3 Resynchronization

If the deserializer loses lock, it automatically tries to re-establish lock. For example, if the embedded clock edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The deserializer then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock edge, identifies it and then proceeds through the locking process. The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid. The system must monitor the LOCK pin to determine whether data on the ROUT is valid.

8.3.4 Pre-Emphasis

The DS90C241 features a pre-emphasis function used to compensate for long or lossy transmission media. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. The transmission distance is limited by the loss characteristics and quality of the media. Pre-emphasis adds extra current during LVDS logic transition to reduce the cable loading effects and increase driving distance. In addition, pre-emphasis helps provide faster transitions, increased eye openings, and improved signal integrity. To enable the pre-emphasis function, the PRE pin requires one external resistor (Rpre) to Vss to set the additional current level. Pre-emphasis strength is set through an external resistor (Rpre) applied from min to max (floating to 3 kΩ) at the PRE pin. A lower input resistor value on the PRE pin increases the magnitude of dynamic current during data transition. There is an internal current source based on the following formula: PRE = (Rpre ≥ 3 kΩ); I_MAX = [(1.2/Rpre) × 20]. The ability of the DS90C241 to use the pre-emphasis feature extends the transmission distance up to 10 meters in most cases.

The amount of pre-emphasis for a given media depends on the transmission distance of the application. In general, too much pre-emphasis can cause over or undershoot at the receiver input pins. This can result in excessive noise, crosstalk and increased power dissipation. For short cables or distances, pre-emphasis may not be required. Signal quality measurements are recommended to determine the proper amount of pre-emphasis for each application.

8.3.5 AC-Coupling and Termination

The DS90C241 and DS90C124 supports AC-coupled interconnects through integrated DC balanced encoding/decoding scheme. To use AC coupled connection between the serializer and deserializer, insert external AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 19. The deserializer input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal V_CM to
1.2 V. With AC signal coupling, capacitors provide the AC-coupling path to the signal input.

For the high-speed LVDS transmissions, the smallest available package must be used for the AC-coupling capacitor. This helps minimize degradation of signal quality due to package parasitics. The most common used capacitor value for the interface is 100-nF (0.1-µF) capacitor. NPO class 1 or X7R class 2 type capacitors are recommended. 50-WVDC must be the minimum used for the best system-level ESD performance.

The DS90C124 input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to 1.2 V. Therefore multiple termination options are possible.

8.3.5.1 Receiver Termination Options

8.3.5.1.1 Option 1

A single, 100-Ω termination resistor is placed across the RIN± pins (see Figure 19). This provides the signal termination at the receiver inputs. Other options may be used to increase noise tolerance.

Figure 19. AC Coupled Application

8.3.5.1.1.1 Option 2

For additional EMI tolerance, two 50-Ω resistors may be used in place of the single 100-Ω resistor. A small capacitor is tied from the center point of the 50-Ω resistors to ground (see Figure 20). This provides a high-frequency low impedance path for noise suppression. Value is not critical; 4.7 nF may be used with general applications.

Figure 20. Receiver Termination Option 2

8.3.5.1.1.2 Option 3

For high noise environments an additional voltage divider network may be connected to the center point. This has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the range of 75 Ω to 2 KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.2 V. For example (see Figure 21), VDD = 3.3 V, Rpullup = 1.3 kΩ, Rpulldown = 750 Ω; or Rpullup = 130 Ω, Rpulldown = 75 Ω (strongest). The smaller values consume more bias current, but provide enhanced noise suppression.

Figure 21. Receiver Termination Option 3

Table 1. DS90C241 Serializer Truth Table

Table 2. DS90C124 Deserializer Truth Table

8.4.1 Power Down

The power-down state is a low power sleep mode that the serializer and deserializer may use to reduce power when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down mode, which reduces supply current to the µA range. The serializer enters power down when the TPWDNB pin is driven low. In power down, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing supply. To exit power down, TPWDNB must be driven high. When the serializer exits power down, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before data transfer can begin. The deserializer enters power down mode when RPWDNB is driven low. In power down mode, the PLL stops and the outputs enter TRI-STATE. To bring the deserializer block out of the power down state, the system drives RPWDNB high.

Both the serializer and deserializer must reinitialize and relock before data can be transferred. The deserializer initializes and asserts LOCK high when it is locked to the input clock.

8.4.2 Tri-State

For the serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This does TRI-STATE both driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer returns to the previous state as long as all other control pins remain static (TPWDNB, TRFB).

When you drive the REN or RPWDNB pin low, the deserializer enters TRI-STATE. Consequently, the receiver output pins (ROUT0 to ROUT23) and RCLK enters TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. The deserializer input pins are high impedance during receiver power down (RPWDNB low) and power-off (V_CC = 0 V).

8.4.3 Progressive Turn–On (PTO)

Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 0.5-UI apart in phase to reduce EMI, simultaneous switching noise, and system ground bounce.