SNLS055J November   1999  – May 2016 DS90CF366 , DS90CF386

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Sequencing and Power-Down Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Cables
        2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
        3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
        4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 20-MHz to 85-MHz Shift Clock Support
  • Rx Power Consumption <142 mW (Typical) at
    85-MHz Grayscale
  • Rx Power-Down Mode <1.44 mW (Maximum)
  • ESD Rating >7 kV (HBM), >700 V (EIAJ)
  • Supports VGA, SVGA, XGA, and Single Pixel SXGA
  • PLL Requires No External Components
  • Compatible With TIA/EIA-644 LVDS Standard
  • Low Profile 56-Pin or 48-Pin TSSOP Package
  • DS90CF386 Also Available in a 64-Pin, 0.8-mm, Fine Pitch Ball Grid Array (NFBGA) Package

2 Applications

  • Video Displays
  • Printers and Imaging
  • Digital Video Transport
  • Machine Vision
  • Open LDI-to-RGB Bridge

3 Description

The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CF366 receiver that converts three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the falling edge. A rising edge or falling edge strobe transmitter will interoperate with a falling edge strobe receiver without any translation logic.

The receiver LVDS clock operates at rates from
20 MHz to 85 MHz. The device phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 85 MHz, each LVDS input line is running at a bit rate of
595 Mbps, resulting in a maximum throughput of
2.38 Gbps for the DS90CF386 and 1.785 Gbps for the DS90CF366.

The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high-speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages. The DS90CF386 is also offered in a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA) package which provides a 44% reduction in PCB footprint compared to the 56-pin TSSOP package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90CF366 TSSOP (48) 12.50 mm × 6.10 mm
DS90CF386 TSSOP (56) 14.00 mm × 6.10 mm
NFBGA (64) 8.00 mm × 8.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Block Diagram (DS90CF366)

DS90CF366 DS90CF386 366_typ_blk_diagram.gif