8.2.2.1 Cables

A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The DS90CF366 requires four pairs of signal wires and the DS90CF386 requires five pairs of signal wires. The ideal cable interface has a constant 100-Ω differential impedance throughout the path. It is also recommended that cable skew remain below 120 ps (assuming 85 MHz clock rate) to maintain a sufficient data sampling window at the receiver.

Depending upon the application and data rate, the interconnecting media between Tx and Rx may vary. For example, for lower data rate (clock rate) and shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed or long distance applications, the media's performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). For example, twin-coax cables have been demonstrated at distances as long as five meters and with the maximum data transfer of 2.38 Gbps (DS90CF366) and 1.785 Gbps (DS90CF386).

8.2.2.2 Bit Resolution and Operating Frequency Compatibility

The bit resolution of the endpoint panel display reveals whether there are enough bits available in the DS90CF386 or DS90CF366 to output the required data per pixel. The DS90CF386 has 28 parallel LVCMOS outputs and can therefore provide a bit resolution up to 24 bpp (bits per pixel). In each clock cycle, the remaining bits are the three control signals (HSync, VSync, DE) and one spare bit. The DS90CF366 has 21 parallel LVCMOS outputs and can therefore provide a bit resolution up to 18 bpp (bits per pixel). In each clock cycle, the remaining bits are the three control signals (HSync, VSync, DE).

The number of pixels per frame and the refresh rate of the endpoint panel display indicate the required operating frequency of the deserializer clock. To determine the required clock frequency, refer to Equation 1.

In each frame, there is a blanking period associated with horizontal rows and vertical columns that are not actively displayed on the panel. These blanking period pixels must be included to determine the required clock frequency. Consider the following example to determine the required LVDS clock frequency:

• H_Active = 640
• H_Blank = 40
• V_Active = 480
• V_Blank = 41
• f_Vertical = 59.95 Hz

Thus, the required operating frequency is determined with Equation 2.

Since the operating frequency for the PLL in the DS90CF386 and DS90CF366 ranges from 20 to 85 MHz, the DS90CF386 and DS90CF366 can support a panel display with the aforementioned requirements.

If the specific blanking interval is unknown, the number of pixels in the blanking interval can be approximated to 20% of the active pixels. Equation 3 can be used as a conservative approximation for the operating LVDS clock frequency:

Using this approximation, the operating frequency for the example in this section is estimated with Equation 4.

8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display

Ensure that the LVCMOS outputs are mapped to align with the endpoint display RGB mapping requirements following the deserializer. See the following for two popular mapping topologies for 8-bit RGB data.

1. LSBs are mapped to RxIN3±.
2. MSBs are mapped to RxIN3±.

Table 2 and Table 3 depict how these two popular topologies can be mapped to the DS90CF386 outputs.

In the case where either DS90CF386 or DS90CF366 is used to support 18 bpp, Table 2 is commonly used, where RxIN3± (if applicable) is left as No Connect. With this mapping, MSBs of RGB data are retained on RXIN0±, RXIN1±, and RXIN2± while the two LSBs for the original 8-bit RGB resolution are ignored from RxIN3±.

8.2.2.4 RSKM Interoperability

One of the most important factors when designing the receiver into a system application is assessing how much RSKM (Receiver Skew Margin) is available. In each LVDS clock cycle, the LVDS data stream carries seven serialized data bits. Ideally, the Transmit Pulse Position for each bit will occur every (n × T)/7 seconds, where
n = Bit Position and T = LVDS Clock Period. Likewise, ideally the Rx Strobe Position for each bit will occur every ((n + 0.5) × T)/7 seconds. However, in real systems, both LVDS Tx and Rx will have non-ideal pulse and strobe position for each bit position due to the effects of cable skew, clock jitter, and ISI. This concept is illustrated in Figure 23.

Figure 23. RSKM Measurement Example

All left and right margins for Bits 0-6 must be considered in order to determine the absolute minimum for the whole LVDS bit stream. This absolute minimum corresponds to the RSKM.

To improve RSKM performance between LVDS transmitter and receiver, designers often either advance or delay the LVDS clock compared to the LVDS data. Moving the LVDS clock compared to the LVDS data can improve the location of the setup and hold time for the transmitter compared to the setup and hold time for the receiver.

If there is less left bit margin than right bit margin, the LVDS clock can be delayed so that the Rx strobe position for incoming data appears to be delayed. If there is less right bit margin than left bit margin, all the LVDS data pairs can be delayed uniformly so that the LVDS clock and Rx strobe position for incoming data appear to advance. To delay an LVDS data or clock pair, designers either add more PCB trace length or install a capacitor between the LVDS transmitter and receiver. It is important to note that when using these techniques, all serialized bit positions are shifted right or left uniformly.

When designing the DS90CF386 or DS90CF366 receiver with a third-party OpenLDI transmitter, users must calculate the skew margin budget (RSKM) based on the Tx pulse position and the Rx strobe position to ensure error-free transmission. For more information about calculating RSKM, refer to Application Note, Receiver Skew Margin for Channel Link I and FPD Link I Devices (SNLA249).