SNLS055J November   1999  – May 2016 DS90CF366 , DS90CF386

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Sequencing and Power-Down Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Cables
        2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
        3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
        4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

As with any high speed design, board designers must maximize signal integrity by limiting reflections and crosstalk that can adversely affect high frequency and EMI performance. The following practices are recommended layout guidelines to optimize device performance.

  • Ensure that differential pair traces are always closely coupled to eliminate noise interference from other signals and take full advantage of the common mode noise canceling effect of the differential signals.
  • Maintain equal length on signal traces for a given differential pair.
  • Limit impedance discontinuities by reducing the number of vias on signal traces.
  • Eliminate any 90º angles on traces and use 45º bends instead.
  • If a via must exist on one signal polarity, mirror the via implementation on the other polarity of the differential pair.
  • Match the differential impedance of the selected physical media. This impedance should also match the value of the termination resistor that is connected across the differential pair at the receiver's input.
  • When possible, use short traces for LVDS inputs.

10.2 Layout Examples

The following images show an example layout of the DS90CF386. Traces in blue correspond to the top layer and the traces in green correspond to the bottom layer. Note that differential pair inputs to the DS90CF386 are tightly coupled and close to the connector pins. In addition, observe that the power supply decoupling capacitors are placed as close as possible to the power supply pins with through vias in order to minimize inductance. The principles illustrated in this layout can also be applied to the 48-pin DS90CF366.

DS90CF366 DS90CF386 ds90cr286q_layout_example.gif Figure 29. Example Layout With DS90CF386 (U1)
DS90CF366 DS90CF386 ds90cr286q_layout_closeup_1.gif Figure 30. Example Layout Close-Up