SNLS672
August 2020 – MONTH
DS90LV028A-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD and Latch-Up Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Performance Curves
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Power Decoupling Recommendations
9.2.2.2
Termination
9.2.2.3
Input Failsafe Biasing
9.2.2.4
Probing LVDS Transmission Lines
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Differential Traces
11.1.2
PC Board Considerations
11.2
Layout Examples
12
Device and Documentation Support
12.1
Support Resources
12.2
Trademarks
12.3
Electrostatic Discharge Caution
12.4
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DQF|8
MPSS009B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls672_oa
snls672_pm
1
Features
AEC-Q100 qualified for automotive applications
Temperature grade 2: -40°C to +105°C
>400 Mbps (200 MHz) switching rates
50 ps differential skew (typical)
0.1 ns channel-to-channel skew (typical)
2.5 ns maximum propagation delay
3.3 V power supply design
Flow-through pinout
Power down high impedance on LVDS inputs
Low power design (18 mW at 3.3 V static)
LVDS inputs accept LVDS/CML/LVPECL signals
Conforms to ANSI/TIA/EIA-644 standard