SNLS201B
September 2005 – January 2019
DS90LV028AH
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Connection Diagram
Functional Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Termination
8.3.2
Threshold
8.3.3
Fail-Safe Feature
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Receiver Bypass Capacitance
9.2.2.2
Interconnecting Media
9.2.2.3
PCB Transmission Lines
9.2.2.4
Input Fail-Safe Biasing
9.2.2.5
Probing LVDS Transmission Lines on PCB
9.2.2.6
Cables and Connectors, General Comments
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Microstrip vs. Stripline Topologies
11.1.2
Dielectric Type and Board Construction
11.1.3
Recommended Stack Layout
11.1.4
Separation Between Traces
11.1.5
Crosstalk and Ground Bounce Minimization
11.1.6
Decoupling
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
D|8
MSOI002K
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls201b_oa
snls201b_pm
1
Features
–40°C to +125°C Operating Temperature Range
>400-Mbps (200-MHz) Switching Rates
50-ps Differential Skew (Typical)
0.1-ns Channel-to-Channel Skew (Typical)
2.5-ns Maximum Propagation Delay
3.3-V Power Supply Design
Flow-Through Pinout
Power Down High Impedance on LVDS Inputs
Low Power Design (18 mW at 3.3-V Static)
LVDS Inputs Accept LVDS/CML/LVPECL Signals
Conforms to ANSI/TIA/EIA-644 Standard
Available in SOIC Package