SNLS728 December   2022 DS90LVRA2

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Decoupling Recommendations
        2. 9.2.2.2 Termination
        3. 9.2.2.3 Input Failsafe Biasing
        4. 9.2.2.4 Probing LVDS Transmission Lines
    3. 9.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Differential Traces
      2. 11.1.2 PC Board Considerations
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DS90LVRA2 is a dual CMOS differential line receiver designed for applications requiring high input common mode range, high data rates and CMOS output with slew rate control. The device is designed to support data rates of 600 Mbps (300 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LVRA2 accepts low voltage (350 mV typical) differential input signals and translates them to 1.8 V CMOS output levels depending on power supply voltage. The DS90LVRA2 has a flow-through design for easy PCB layout.

The DS90LVRA2 and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

Package Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
DS90LVRA2DEM (WSON, 8)2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-4F112770-4856-448F-A197-479AA8C66C67-low.gif Functional Diagram