SNLS708 February 2023 DS90UB638-Q1
PRODUCTION DATA
The following interrupts are available for each CSI-2 Transmit Port:
See the CSI_TX_ICR address 0x36 and CSI_TX_ISR address 0x37 registers for details.
The setting of the individual interrupt status bits is not dependent on the related interrupt enable controls. The interrupt enable controls whether an interrupt is generated based on the condition, but does not prevent the interrupt status assertion.