SNLS708 February 2023 DS90UB638-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | PIN OR FREQUENCY | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
TOTAL POWER CONSUMPTION | ||||||||
PT | Total power consumption for MIPI CSI-2 output mode, normal operation | FPD-Link III Input, FPD-Link III line-rate
= 4.0 Gbps CSI-2 line-rate = 1.6 Gbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL = LOW, default registers |
V(VDD18)= 1.89 V, V(VDDIO) = 3.6 V | 473 | 564 | mW | ||
FPD-Link III Input, FPD-Link III line-rate
= 4.0 Gbps CSI-2 line-rate = 1.6 Gbps, CS-I2 = 4 DATA lanes + 1 CLK lane VDD_SEL = HIGH, default registers |
V(VDD18)= 1.89 V, V(VDD11) = 1.155 V V(VDDIO) = 3.6 V | 450 | mW | |||||
DESERIALIZER SUPPLY CURRENT - FPD-Link III Rx Port0 WITH DS90UB635 | ||||||||
IDD-R1T4 | Deserializer supply current 1 Rx 4 Tx | 1 x FPD-Link III Input, FPD-Link III line-rate = 4.0 Gbps CSI-2 line-rate = 800 Mbps per lane, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, default registers, includes CSI-2 load current |
VDD18 | 170 | 188 | mA | ||
VDDIO | 5 | 10 | ||||||
1 x FPD-Link III Input, FPD-Link III line-rate = 4.0 Gbps CSI-2 line-rate = 800 Mbps per lane, CSI2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, default registers, includes CSI-2 load current |
VDD18 | 65 | 80 | mA | ||||
VDD11 | 80 | 100 | ||||||
VDDIO | 5 | 10 | ||||||
DESERIALIZER SUPPLY CURRENT - FPD-Link III Rx Port0 WITH DS90UB633A | ||||||||
IDD2-R1T4 | Deserializer supply current 2G 1 Rx 4 Tx | 1 x FPD-Link III Input, FPD-Link III line-rate = 1.867 Gbps CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, includes CSI-2 load current |
VDD18 | 150 | 205 | mA | ||
VDDIO | 5 | 10 | ||||||
1 x FPD-Link III Input, FPD-Link III line-rate = 1.867 Gbps CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, includes CSI-2 load current |
VDD18 | 65 | 86 | mA | ||||
VDD11 | 75 | 110 | ||||||
VDDIO | 5 | 10 | ||||||
DESERIALIZER SUPPLY CURRENT - Power Down |
||||||||
IDDZ | Deserializer shutdown current | PDB = HIGH to LOW, VDD_SEL = LOW | VDD18 | 82 | 115 | mA | ||
VDIO | 2.5 | 5 | ||||||
PDB = HIGH to LOW, VDD_SEL = HIGH | VDD18 | 10 | 15 | |||||
VDD11 | 30 | 110 | ||||||
VDDIO | 2.5 | 5 | ||||||
1.8-V LVCMOS I/O | ||||||||
VOH | High level output voltage | IOH = –2 mA, V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:4], GPIO[2:0], LOCK, PASS | V(VDDIO) – 0.45 | V(VDDIO) | V | ||
VOL | Low level output voltage | IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:0], LOCK, PASS | GND | 0.45 | V | ||
VIH | High level input voltage | V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:0], BISTEN | 0.65 × V(VDDIO) |
V(VDDIO) | V | ||
V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | PDB, VDD_SEL | 1.17 | V(VDDIO) | V | ||||
V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV | XIN/REFCLK | 1.15 | V(VDDIO) | V | ||||
VIL | Low level input voltage | V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18 ±50 mV | GPIO[6:0], BISTEN | GND | 0.35 × V(VDDIO) |
V | ||
V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18 ±50 mV | PDB, VDD_SEL | GND | 0.63 | V | ||||
V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18 ±50 mV | XIN/REFCLK | GND | 0.7 | V | ||||
IIH | Input high current | VIN = V(VDDIO) = 1.71 to 1.89 V, | Internal pulldown enabled | GPIO[6:0], PDB, BISTEN | –100 | 100 | μA | |
IIH | Input high current | VIN = V(VDDIO) = 1.71 to 1.89 V, | Internal pulldown disabled | GPIO[6:0], XIN/REFCLK, VDD_SEL | –20 | 30 | μA | |
IIL | Input low current | VIN = 0V | GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN | –20 | 30 | μA | ||
IOS | Output short circuit current | VOUT = 0 V | VOUT = 0 V | –25 | mA | |||
IOZ | TRI-STATE Output Current | VOUT = 0 V or VDDIO, PDB = L | VOUT = 0 V or VDDIO, PDB = L | –25 | 25 | μA | ||
3.3-V LVCMOS I/O | ||||||||
VOH | High level output voltage | IOH = –4 mA, V(VDDIO) = 3.0 to 3.6 V | GPIO[6:4], GPIO[2:0], LOCK, PASS | 2.4 | V(VDDIO) | V | ||
VOL | Low level output voltage | IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V | GPIO[6:0], LOCK, PASS | GND | 0.4 | V | ||
VIH | High level input voltage | V(VDDIO) = 3 to 3.6 V | GPIO[6:0], XIN/REFCLK, VDD_SEL, BISTEN | 2 | V(VDDIO) | V | ||
V(VDDIO) = 3 to 3.6 V | PDB, VDD_SEL | 1.17 | V(VDDIO) | V | ||||
V(VDDIO) = 3 to 3.6 V | XIN/REFCLK | 1.15 | V(VDDIO) | V | ||||
VIL | Low level input voltage | V(VDDIO) = 3 to 3.6 V | GPIO[6:0], XIN/REFCLK, VDD_SEL, BISTEN | GND | 0.8 | V | ||
V(VDDIO) = 3 to 3.6 V | PDB, VDD_SEL | GND | 0.63 | V | ||||
V(VDDIO) = 3 to 3.6 V | XIN/REFCLK | GND | 0.7 | V | ||||
IIH | Input high current | VIN = 3 to 3.6 V, internal pulldown enabled | GPIO[6:0], PDB, BISTEN | –190 | 190 | μA | ||
VIN = 3 to 3.6 V, internal pulldown disabled | GPIO[6:0], XIN/REFCLK, VDD_SEL | –20 | 30 | μA | ||||
IIL | Input low current | VIN = 0 V | GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN | –20 | 30 | μA | ||
IOS | Output short circuit current | VOUT = 0 V | GPIO[7:0], LOCK, PASS | –40 | mA | |||
IOZ | TRI-STATE output current | VOUT = 0 V or V(VDDIO), PDB = L | GPIO[7:0], LOCK, PASS | –25 | 35 | μA | ||
SERIAL CONTROL BUS(1) | ||||||||
VIH | Input high level | I2C_SDA, I2C_SCL | 0.7 × V(I2C) | V(I2C) | V | |||
VIL | Input low level | GND | 0.3 × V(I2C) | V | ||||
VHY | Input hysteresis | 50 | mV | |||||
VOL | Output low level | Standard-mode/Fast-mode IOL = 3 mA | 0 | 0.4 | V | |||
Fast-mode Plus IOL = 20 mA | 0 | 0.4 | V | |||||
IIH | Input high current | VIN = V(I2C) | –10 | 10 | µA | |||
IIL | Input low current | VIN = 0V | –10 | 10 | µA | |||
CIN | Input capacitance | 5 | pF | |||||
FPD-LINK III INPUT |
||||||||
VCM | Common mode voltage | RIN0+, RIN0- |
1.2 | V | ||||
RT | Internal termination resistor | Single-ended | RIN0+ | 40 | 50 | 60 | Ω | |
Differential | RIN0+, RIN0- |
80 | 100 | 120 | Ω | |||
FPD-LINK III BIDIRECTIONAL CONTROL CHANNEL | ||||||||
VOUT-BC | Back Channel Output Single-ended voltage | RL = 50 Ω, coaxial configuration, forward channel disabled | RIN0+, RIN0- |
190 | 225 | 260 | mV | |
VOD-BC | Back channel output differential | RL = 100 Ω, STP configuration, forward channel disabled | 380 | 450 | 520 | mV | ||
HSTX DRIVER |
||||||||
VCMTX | HS transmit static common-mode voltage | CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLK1P/N, CSI_CLK0P/N | 150 | 200 | 250 | mV | ||
|ΔVCMTX(1,0)| | VCMTX mismatch when output is 1 or 0 | 5 | mVP-P | |||||
|VOD| | HS transmit differential voltage | 140 | 200 | 270 | mV | |||
|ΔVOD| | VOD mismatch when output is 1 or 0 | 14 | mV | |||||
VOHHS | HS output high voltage | 360 | mV | |||||
ZOS | Single-ended output impedance | 40 | 50 | 62.5 | Ω | |||
ΔZOS | Mismatch in single-ended output impedance | 10 | % | |||||
LPTX DRIVER |
||||||||
VOH | High level output voltage | Applicable when the supported data rate is ≤ 1.5 Gbps | CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLK1P/N, CSI_CLK0P/N | 1.1 | 1.2 | 1.3 | V | |
Applicable when the supported data rate is > 1.5 Gbps | 0.95 | 1.3 | V | |||||
VOL | Low level output voltage | -50 | 50 | mV | ||||
ZOLP | Output impedance | 110 | Ω |