SNLS499D April   2016  – October 2019 DS90UB914A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DS90UB914A-Q1 Deserializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
    7. 7.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams and Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Frame Format
      2. 9.3.2  Line Rate Calculations for the DS90UB913A/914A
      3. 9.3.3  Deserializer Multiplexer Input
      4. 9.3.4  Error Detection
      5. 9.3.5  Synchronizing Multiple Cameras
      6. 9.3.6  General-Purpose I/O (GPIO) Descriptions
      7. 9.3.7  LVCMOS VDDIO Option
      8. 9.3.8  EMI Reduction
        1. 9.3.8.1 Deserializer Staggered Output
        2. 9.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
      9. 9.3.9  Pixel Clock Edge Select (TRFB / RRFB)
      10. 9.3.10 Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 DS90UB913A/914A Operation With External Oscillator as Reference Clock
      2. 9.4.2 DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
      3. 9.4.3 MODE Pin on Deserializer
      4. 9.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      5. 9.4.5 Built-In Self Test
      6. 9.4.6 BIST Configuration and Status
      7. 9.4.7 Sample BIST Sequence
    5. 9.5 Programming
      1. 9.5.1 Programmable Controller
      2. 9.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 9.5.3 I2C Pass-Through
      4. 9.5.4 Slave Clock Stretching
      5. 9.5.5 ID[x] Address Decoder on the Deserializer
      6. 9.5.6 Multiple Device Addressing
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Over Coax
      2. 10.1.2 Power-Up Requirements and PDB Pin
      3. 10.1.3 AC Coupling
      4. 10.1.4 Transmission Media
      5. 10.1.5 Adaptive Equalizer – Loss Compensation
    2. 10.2 Typical Applications
      1. 10.2.1 Coax Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 STP Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Interconnect Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVCMOS DC SPECIFICATIONS 3.3-V I/O (DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH High Level Input Voltage VIN = 3 V to 3.6 V 2 VIN V
VIL Low Level Input Voltage VIN = 3 V to 3.6 V GND 0.8 V
IIN Input Current VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V –20 ±1 20 µA
VOH High Level Output Voltage VDDIO = 3 V to 3.6 V, IOH = −4 mA 2.4 VDDIO V
VOL Low Level Output Voltage VDDIO = 3 V to 3.6 V, IOL = 4 mA GND 0.4 V
IOS Output Short Circuit Current VOUT = 0 V Deserializer
GPO Outputs		 –15 mA
LVCMOS Outputs –35
IOZ TRI-STATE Output Current PDB = 0 V,
VOUT = 0 V or VDD 		LVCMOS Outputs, GPO Outputs –20 20 µA
CGPIO Pin Capacitance GPIO [3:0] 1.5 pF
LVCMOS DC SPECIFICATIONS 1.8-V I/O (DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH High Level Input Voltage VIN = 1.71 V to 1.89 V 0.65 VIN VIN V
VIL Low Level Input Voltage VIN = 1.71 V to 1.89 V GND 0.35 VIN
IIN Input Current VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V –20 ±1 20 µA
VOH High Level Output Voltage VDDIO = 1.71 V to 1.89 V, IOH = −4 mA VDDIO – 0.45 VDDIO V
VOL Low Level Output Voltage VDDIO = 1.71 V to 1.89 V IOL = 4 mA GND 0.45 V
IOS Output Short Circuit Current VOUT = 0 V Deserializer
GPO Outputs		 –11 mA
LVCMOS Outputs –17
IOZ TRI-STATE Output Current PDB = 0 V,
VOUT = 0 V or VDD 		LVCMOS Outputs, GPO Outputs -20 20 µA
CGPIO Pin Capacitance GPIO [3:0] 1.5 pF
CML RECEIVER DC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )
IIN Input Current VIN = VDD or 0 V, VDD = 1.89 V, –20 1 20 µA
RT Differential Internal Termination Resistance Differential across RIN+ and RIN– 80 100 120 Ω
Single-ended
Termination Resistance		 RIN+ or RIN– 40 50 60
VID Differential Input Voltage Back Channel Disabled, (Figure 4) 210 mV
VIN Single-Ended Input Voltage Back Channel Disabled, (Figure 4) 105 mV
ƒBC Back Channel Frequency(7) 3.3 4.2 MHz
VOD-BC Back Channel Differential Output Voltage 350 540 mV
VOUT-BC Back Channel Single-Ended Output Voltage 182 270 mV
CML MONITOR OUTPUT DRIVER SPECIFICATIONS (CMLOUTP, CMLOUTN)
Ew Differential Output
Eye Opening(5) 		RL = 100 Ω
Jitter Frequency > f/15 (Figure 9) 		0.45 UI
EH Differential Output
Eye Height		 200 mV
DESERIALIZER SUPPLY CURRENT
IDDIOR Deserializer (Rx)
Total Supply Current
(includes load current)		 VDDIO=1.89 V
CL=8 pF
Worst Case Pattern 		f = 100 MHz,
10–bit mode		 22 42 mA
f = 75 MHz, 12–bit high freq mode 19 39
f = 50 MHz, 12–bit low freq mode 16 32
VDDIO=1.89 V
CL=8 pF
Random Pattern 		f = 100 MHz,
10–bit mode		 15 mA
f = 75 MHz, 12–bit high freq mode 12
f = 50 MHz, 12–bit low freq mode 10
VDDIO=3.6 V
CL=8 pF
Worst Case Pattern		 f = 100 MHz,
10–bit mode		 42 55 mA
f = 75 MHz, 12–bit high freq mode 37 50
f = 50 MHz, 12–bit low freq mode 25 38
VDDIO= 3.6 V
CL= 8 pF
Random Pattern		 f = 100 MHz,
10–bit mode		 35 mA
f = 75 MHz, 12–bit high freq mode 30
f = 50 MHz, 12–bit low freq mode 18
VDDIO= 1.89 V
CL= 4 pF
Worst Case Pattern		 f = 100 MHz,
10–bit mode		 15 mA
f = 75 MHz, 12–bit high freq mode 11
f = 50 MHz, 12–bit low freq mode 16
VDDIO= 1.89 V
CL= 4 pF
Random Pattern 		f = 100 MHz,
10–bit mode		 8 mA
f = 75 MHz, 12–bit high freq mode 4
f = 50 MHz, 12–bit low freq mode 9
VDDIO= 3.6 V
CL= 4 pF
Worst Case Pattern		 f = 100 MHz,
10–bit mode		 36 mA
f = 75 MHz, 12–bit high freq mode 29
f = 50 MHz, 12–bit low freq mode 20
VDDIO= 3.6 V
CL= 4 pF
Random Pattern		 f = 100 MHz, 10–bit mode 29 mA
f = 75 MHz, 12–bit high freq mode 22
f = 50 MHz, 12–bit low freq mode 13
IDDR Deserializer (Rx) VDD_n Supply Current (includes load current) VDD_n = 1.89 V
CL= 4 pF
Worst Case Pattern		 f = 100 MHz,
10–bit mode		 64 110 mA
f = 75 MHz,
12–bit high freq mode		 67 114
f = 50 MHz,
12–bit low freq mode		 63 96
VDD_n= 1.89 V
CL= 4 pF
Random Pattern		 f = 100 MHz,
10–bit mode		 69
f = 75 MHz,
12–bit high freq mode		 71
f = 50 MHz,
12–bit low freq mode		 67
IDDRZ Deserializer (Rx) Supply Current Power Down PDB = 0 V, All other LVCMOS Inputs=0 V VDDIO = 1.89 V
Default Registers		 42 900 µA
PDB = 0 V, All other LVCMOS Inputs = 0 V VDDIO=3.6 V
Default Registers		 42 900
IDDIORZ Deserializer (Rx) VDDIO Supply Current Power Down PDB = 0 V, All other LVCMOS Inputs = 0 V VDDIO = 1.89 V 8 40 µA
VDDIO = 3.6 V 360 800