SNLS507C September   2016  – December 2022 DS90UB934-Q1

PRODUCTION DATA  

  1.   Features
  2. 1Applications
  3. 2Description
  4. 3Revision History
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Electrical Characteristics
    6. 4.6 AC Electrical Characteristics
    7. 4.7 Recommended Timing for the Serial Control Bus
    8. 4.8 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Serial Frame Format
      2. 5.3.2 Line Rate Calculations for the DS90UB933/934
      3. 5.3.3 Deserializer Multiplexer Input
    4. 5.4 Device Functional Modes
      1. 5.4.1 RX MODE Pin
      2. 5.4.2 DVP Output Control
        1. 5.4.2.1 LOCK Status
      3. 5.4.3 Input Jitter Tolerance
      4. 5.4.4 Adaptive Equalizer
      5. 5.4.5 Channel Monitor Loop-Through Output Driver
        1. 5.4.5.1 Code Example for CMLOUT FPD3 RX Port 0:
      6. 5.4.6 GPIO Support
        1. 5.4.6.1 Back Channel GPIO
        2. 5.4.6.2 GPIO Pin Status
        3. 5.4.6.3 Other GPIO Pin Controls
        4. 5.4.6.4 FrameSync Operation
          1. 5.4.6.4.1 External FrameSync Control
          2. 5.4.6.4.2 Internally Generated FrameSync
            1. 5.4.6.4.2.1 Code Example for Internally Generated FrameSync
    5. 5.5 Programming
      1. 5.5.1 Serial Control Bus
        1. 5.5.1.1 I2C Target Operation
        2. 5.5.1.2 Remote Target Operation
        3. 5.5.1.3 Remote I2C Targets Data Throughput
        4. 5.5.1.4 Remote Target Addressing
        5. 5.5.1.5 Broadcast Write to Remote Target Devices
        6. 5.5.1.6 Code Example for Broadcast Write
      2. 5.5.2 Interrupt Support
        1. 5.5.2.1 Code Example to Enable Interrupts
        2. 5.5.2.2 FPD-Link III Receive Port Interrupts
        3. 5.5.2.3 Code Example to Readback Interrupts
        4. 5.5.2.4 Built-In Self Test (BIST)
          1. 5.5.2.4.1 BIST Configuration and Status
    6. 5.6 Register Maps
      1. 5.6.1 Register Description
      2. 5.6.2 Registers
      3. 5.6.3 Indirect Access Registers
      4. 5.6.4 Indirect Access Register Map
        1. 5.6.4.1 FPD3 Channel 0 Registers
        2. 5.6.4.2 FPD3 Channel 1 Registers
        3. 5.6.4.3 FPD3 RX Shared Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Over Coax
    3. 6.3 Typical Application
      1. 6.3.1 Design Requirements
      2. 6.3.2 Detailed Design Procedure
      3. 6.3.3 Application Curves
    4. 6.4 System Examples
    5. 6.5 Power Supply Recommendations
      1. 6.5.1 VDD Power Supply
      2. 6.5.2 Power-Up Sequencing
      3. 6.5.3 PDB Pin
      4. 6.5.4 Ground
    6. 6.6 Layout
      1. 6.6.1 Layout Guidelines
        1. 6.6.1.1 DVP Interface Guidelines
      2. 6.6.2 Layout Example
  9.   Mechanical, Packaging, and Orderable Information
  10. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Glossary
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-6B91E35C-2775-4E6A-B9F4-FB385B767B46-low.gif Figure 4-1 RGZ Package48-Pin VQFN With Thermal Pad Top View
Table 4-1 Pin Functions
PIN I/O
TYPE		 DESCRIPTION
NAME NO.
RECEIVE DATA PARALLEL OUTPUT
ROUT0 24 O RECEIVE DATA OUTPUT: This signal carries data from the FPD-LINK III deserializer to the processor. Output is parallel, configurable for up to 12 bits (ROUT0 – ROUT11) single ended outputs. VDDIO logic levels. For unused outputs leave as No Connect.
ROUT1 23
ROUT2 22
ROUT3 21
ROUT4 19
ROUT5 18
ROUT6 16
ROUT7 15
ROUT8 14
ROUT9 13
ROUT10 12
ROUT11 11
HSYNC 10 O Horizontal SYNC output. VDDIO logic levels.
VSYNC 9 O Vertical SYNC output. VDDIO logic levels.
PCLK 8 O Pixel clock (PCLK) output. VDDIO logic levels.
GPIO
GPIO0 28 I/O, PD General purpose input/output: Pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPOs on the serializer or they may be configured to be outputs to follow local register settings. At power up the GPIO are disabled and by default include a 25-kΩ (typical) pulldown resistor. VDDIO logic levels. Unused GPIOs can be left open or floating.
GPIO1 27
GPIO2 26
GPIO3/INTB 25 I/O, Open Drain General purpose input/output: Pin GPIO3 can be configured to be an input signal for GPOs on the serializer. Pin 25 is shared with INTB. Pull up with 4.7 kΩ to VI2C. Programmable input/output pin is an active-low open drain and controlled by the status registers. The INTB VIH and VIL thresholds will be set based on the VDDIO voltage as the default and can be reprogrammed by the IO_CTL register. Unused GPIOs can be left open or floating.
FPD-LINK III INTERFACE
RIN0+ 41 I/O Receive input channel 0: Differential FPD-Link receiver and bidirectional control back channel output. The IO must be AC coupled. There is internal 100Ω differential termination between RIN0+ and RIN0-. For applications using single-ended coaxial channel connect RIN0+ with 100-nF, AC-coupling capacitor and terminate RIN0– to GND with a 47-nF capacitor and 50-Ω resistor. For STP applications connect both RIN0+ and RIN0- with 100-nF, AC-coupling capacitor.
RIN0– 42
RIN1+ 32 I/O Receive input channel 1: Differential FPD-Link receiver and bidirectional control back channel output. The IO must be AC coupled. There is internal 100Ω differential termination between RIN1+ and RIN1–. For applications using single-ended coaxial channel connect RIN0+ with 100nF AC coupling capacitor and terminate RIN1- to Ground with a 47 nF capacitor and 50 ohm resistor. For STP applications connect both RIN1+ and RIN1– with 100 nF AC coupling capacitor.
RIN1– 33
I2C PINS
I2C_SCL 2 I/O,
Open Drain		 I2C serial clock: Clock line for the bidirectional control bus communication.
External 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended per I2C interface standards. The I2C VIH and VIL thresholds will be set based on the VDDIO voltage as the default and can be reprogrammed by the IO_CTL register.
I2C_SDA 1 I/O,
Open Drain		 I2C serial data: Data line for bidirectional control bus communication.
External 2-kΩ to 4.7-kΩ pullup resistor to VI2C recommended per I2C interface standards. The I2C VIH and VIL thresholds will be set based on the VDDIO voltage as the default and can be reprogrammed by the IO_CTL register.
CONFIGURATION and CONTROL PINS
IDX 35 S Input. I2C serial control bus device ID address
Connect to external pullup to VDD18 (pin 17) and pull down to GND to create a voltage divider. See Table 5-7.
MODE 37 S Mode select configuration input to set operating mode based on input voltage level.
Typically connected to voltage divider via external pullup to VDD18 (pin 17) and pulldown to GND See Table 5-2.
PDB 30 S, PD Power-down inverted Input Pin. This pin is internal pull down enabled. When PDB input is brought HIGH, the device is enabled. Asserting PDB signal low powers down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN. This pin has a 50-kΩ (typical) internal pulldown resistor. INPUT IS 3.3 V TOLERANT.
PDB = 1.8 V, device is enabled (normal operation)
PDB = 0, device is powered down.
SEL 46 S,PD MUX select: Digital input for selecting FPD Link input channel 0 (A) or channel 1 (B). The default state of SEL = L, selects RIN0, input A, as the active channel on the deserializer. Asserting SEL = H selects RIN1 input B as the active channel on the deserializer. This pin has a 25-kΩ (typical) internal pulldown resistor. VDDIO logic levels.
OSS_SEL 4 S, PD Output sleep state select pin for enabling output sleep state. This pin has a 25-kΩ (typical) internal pulldown resistor. If unused, connect to VDD. If using pullup resistor to connect to VDD, the resistor value should be <= 4.3-kΩ. VDDIO logic levels. See Section 5.4.2.
OEN 5 S, PD Output enable. This pin has a 1-MΩ (typical) internal pulldown resistor. If unused, connect to VDD. If using pullup resistor to connect to VDD, the resistor value should be <= 4.3-kΩ. VDDIO logic levels. See Section 5.4.2.
DIAGNOSTIC PINS
CMLOUTP 38 O Channel monitor loop-through (CML) driver differential output. Typically routed to test points and not connected. For monitoring terminate CMLOUT with a 100-Ω differential load.
CMLOUTN 39
BISTEN 6 S, PD BIST enable: BISTEN = H, BIST mode is enabled BISTEN = L, BIST mode is disabled. See Section 5.5.2.4 for more information. This pin has a 25-kΩ (typ) internal pulldown resistor. VDDIO logic levels.
PASS 47 O PASS Output: PASS = H, ERROR FREE transmission in forward channel operation. PASS = L, one or more errors were detected in the received payload. See Section 5.5.2.4 for more information. Leave No Connect if unused. Typically route to test point for monitoring. VDDIO logic levels.
LOCK 48 O LOCK Status: Output pin for monitoring lock status of FPD-Link III channel. LOCK = H, PLL is Locked, outputs are active. LOCK = L, PLL is unlocked, may be used as link status. VDDIO logic levels.
RES 44 - Reserved. Must be NC or tied to GND for normal operation.
RES 43 - Reserved. This pin has internal pull-up resistor. Must be tied to GND for normal operation.
POWER AND GROUND
VDDIO 7,29 P VDDIO voltage supply input: The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8-V, ±5% or 3-V to 3.6-V power rail. Each pin requires a minimum 10-nF capacitor to GND.
VDD18 17 P 1.8-V (±5%) power supply.
Requires 1-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin.
VDD18_P0
VDD18_P1		 45
36		 P 1.8-V (±5%) PLL power supplies.
Requires 1-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin.
VDD18_FPD0
VDD18_FPD1		 40
31		 P 1.8-V (±5%) high-speed transceiver (HSTRX) analog power supplies.
Requires 10-μF, 0.1-μF, and 0.01-μF capacitors to GND at each VDD pin.
VDD11_FPD 34 D Decoupling capacitor connection for internal analog regulator. Requires a minimum 4.7-μF capacitor to GND and must not be connected to other 1.1-V supply rails.
VDD11_DVP 20 D Decoupling capacitor connection for internal mixed signal regulator. Requires a minimum 4.7-μF capacitor to GND and must not be connected to other 1.1-V supply rails.
VDD11_D 3 D Decoupling capacitor connection for internal digital regulator. Requires a minimum 4.7-μF capacitor to GND and must not be connected to other 1.1-V supply rails.
GND DAP G DAP is the large metal contact at the bottom side, located at the center of the QFN package. Connect to the ground plane (GND).
The definitions below define the functionality of the I/O cells for each pin. TYPE:
  • I = Input
  • O = Output
  • I/O = Input/Output
  • S = Configuration pin (All strap pins have internal pulldowns. If the default strap value needs to be changed then use an external resistor.)
  • PD = Internal pulldown
  • P, G = Power supply, ground
  • D = Decoupling pin for internal voltage rail