SNLS507 Data sheet

SNLS507C September 2016 – December 2022 DS90UB934-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGZ|48
- MPQF123F

Thermal pad, mechanical data (Package|Pins)

RGZ|48
- QFND014T

Orderable Information

5.6.2 Registers

Table 5-10 Serial Control Bus Registers

Page	Addr (hex)	Register Name	Bit(s)	Field	Type	Default	Description
Share	0x00	I2C Device ID	7:1	DEVICE ID	(R/W)/S	0x3D	7-bit I2C ID of deserializer Defaults to address configured by IDX strap pin. This field always indicates the current value of the I2C ID. When bit 0 of this register is 0, this field is read-only and shows the strapped ID. When bit 1 of this register is 1, this field is read/write and can be used to assign any valid I2C ID.
			0	DES ID	R/W	0x0	0: Device ID is from IDX strap pin 1: Register I2C device ID overrides strapped value
Share	0x01	Reset	7:3	RESERVED	R/W	0x0	Reserved
			2	RESTART_AUTOLOAD	(R/W)/SC	0x0	Restart ROM auto-load Setting this bit to 1 causes a re-load of the ROM. This bit is self-clearing. Software may check for auto-load complete by checking the CFG_INIT_DONE bit in the DEVICE_STS register.
			1	DIGITAL RESET1	(R/W)/SC	0x0	Digital reset Resets the entire digital block including registers. This bit is self-clearing. 1: Reset 0: Normal operation
			0	DIGITAL RESET0	(R/W)/SC	0x0	Digital reset Resets the entire digital block except registers. This bit is self-clearing. 1: Reset 0: Normal operation
Share	0x02	General Configuration	7	INPUT_PORT_OVERRIDE	R/W	0x0	Input port override bit allows control of the input port selection via the INPUT_PORT_SEL bit in this register.
			6	INPUT_PORT_SEL	R/W	0x0	Input port select. This bit either controls the input mode (if INPUT_PORT_OVERRIDE is set) or indicates the status of the SEL pin.
			5	OUTPUT_OVERRIDE	R/W	0x0	Output Control Override bit. The OUTPUT_ENABLE and OUTPUT_SLEEP_STATE_SEL values typically come from the device input pins. If this bit is set, the register values in this register will be used instead.
			4	RESERVED	R/W	0x1	Reserved
			3	OUTPUT_ENABLE	R/W	0x1	Output enable control (in conjunction with output sleep state select) If OUTPUT_SLEEP_STATE_SEL is set to 1 and this bit is set to 0, the TX outputs will be forced into a high impedance state. If OUTPUT_OVERRIDE is 0, this register indicates the value on the OEN pin. See Table 5-3.
			2	OUTPUT_SLEEP_STATE_SEL	R/W	0x1	OSS Select controls the output state when LOCK is low (used in conjunction with Output Enable) When this bit is set to 0, the TX outputs is forced into a HS-0 state. If OUTPUT_OVERRIDE is 0, this register indicates the value on the OSS_SEL pin. See Table 5-3.
			1	RX_PARITY_CHECKER_EN	R/W	0x1	FPD3 Receiver Parity Checker Enable. When enabled, the parity check function is enabled for the FPD3 receiver. This allows detection of errors on the FPD3 receiver data bits. 0: Disable 1: Enable
			0	Reserved	R/W	0x0	Reserved
Share	0x03	Revision/Mask ID	7:4	REVISION_ID	R	0x0	Revision ID 0000: Production release
			3:0	RESERVED	R	0x0	Reserved
Share	0x04	DEVICE_STS	7	CFG_CKSUM_STS	R	0x1	Config Checksum passed This bit is set following initialization if the configuration data in the eFuse ROM had a valid checksum
			6	CFG_INIT_DONE	R	0x1	Power-up initialization complete This bit is set after Initialization is complete. Configuration from eFuse ROM has completed.
			5:4	RESERVED	R	0x0	Reserved
			3	PASS	R, LH	0x0	Device PASS status This bit indicates the PASS status for the device. The value in this register matches the indication on the PASS pin.
			2	LOCK	R, LH	0x0	Device LOCK status This bit indicates the LOCK status for the device. The value in this register matches the indication on the LOCK pin.
			1:0	RESERVED	R	0x0	Reserved
Share	0x05	PAR_ERR_THOLD_HI	7:0	PAR_ERR_THOLD_HI	R/W	0x01	FPD3 parity error threshold high byte This register provides the 8 most significant bits of the parity error threshold value. For each port, if the FPD-Link III receiver detects a number of parity errors greater than or equal to this value, the PARITY_ERROR flag is set in the RX_PORT_STS1 register.
Share	0x06	PAR_ERR_THOLD_LO	7:0	PAR_ERR_THOLD_LO	R/W	0x0	FPD3 parity error threshold low byte This register provides the 8 least significant bits of the parity error threshold value. For each port, if the FPD-Link III receiver detects a number of parity errors greater than or equal to this value, the PARITY_ERROR flag is set in the RX_PORT_STS1 register.
Share	0x07	BCC Watchdog Control	7:1	BCC WATCHDOG TIMER	R/W	0x7F	The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the bidirectional control channel watchdog timeout value in units of 2 milliseconds. Do not set this field to 0.
			0	BCC WATCHDOG TIMER DISABLE	R/W	0x0	Disable bidirectional control channel watchdog timer 1: Disables BCC watchdog timer operation 0: Enables BCC watchdog timer operation
Share	0x08	I2C Control 1	7	LOCAL WRITE DISABLE	R/W	0x0	Disable remote writes to local registers Setting this bit to a 1 prevents remote writes to local device registers from across the control channel. This prevents writes to the deserializer registers from an I2C controller attached to the serializer. Setting this bit does not affect remote access to I2C targets at the deserializer.
			6:4	I2C SDA HOLD	R/W	0x1	Internal SDA hold time This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 nanoseconds.
			3:0	I2C FILTER DEPTH	R/W	0xC	I2C glitch filter depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 nanoseconds.
Share	0x09	I2C Control 2	7:4	SDA Output Setup	R/W	0x1	Remote Ack SDA output setup When a control channel (remote) access is active, this field configures setup time from the SDA output relative to the rising edge of SCL during ACK cycles. Setting this value will increase setup time in units of 640ns. The nominal output setup time value for SDA to SCL when this field is 0 is 80 ns.
			3:2	SDA Output Delay	R/W	0x0	SDA output delay This field configures additional delay on the SDA output relative to the falling edge of SCL. Setting this value increases output delay in units of 40 ns. Nominal output delay values for SCL to SDA are: 00: 240 ns 01: 280 ns 10: 320 ns 11: 360 ns
			1	I2C BUS TIMER SPEEDUP	R/W	0x0	Speed up I2C bus watchdog timer 1: Watchdog Timer expires after approximately 50 microseconds 0: Watchdog Timer expires after approximately 1 second.
			0	I2C BUS TIMER DISABLE	R/W	0x0	Disable I2C bus watchdog timer When enabled the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1 second, the I2C bus is assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL.
Share	0x0A	SCL High Time	7:0	SCL HIGH TIME	R/W	0x7A	I2C controller SCL high time This field configures the high pulse width of the SCL output when the Serializer is the controller on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. Nominal High Time = 40 ns × (TX_SCL_HIGH + 4) The internal oscillator has ±10% variation which must be taken into account when setting the SCL High and Low Time registers.
Share	0x0B	SCL Low Time	7:0	SCL LOW TIME	R/W	0x7A	I2C SCL low time This field configures the low pulse width of the SCL output when the serializer is the controller on the local I2C bus. This value is also used as the SDA setup time by the I2C target for providing data prior to releasing SCL during accesses over the Bidirectional control channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional clock periods. Nominal low time = 40 ns × (TX_SCL_LOW + 4) The internal oscillator has ±10% variation which must be taken into account when setting the SCL High and Low Time registers.
Share	0x0C	RESERVED	7:0	RESERVED	R/W	0x0	Reserved
Share	0x0D	IO_CTL	7	SEL3P3V	R/W	0x0	3.3-V I/O Select on pins INTB, I2C 0: 1.8-V I/O Supply 1: 3.3-V I/O Supply If IO_SUPPLY_MODE_OV is 0, a read of this register returns the detected VDDIO voltage level.
			6	IO_SUPPLY_MODE_OV	R/W	0x0	Override I/O Supply Mode bit If set to 0, the detected VDDIO voltage level is used for both SEL3P3V and IO_SUPPLY_MODE controls. If set to 1, the values written to the SEL3P3V and IO_SUPPLY_MODE fields is used.
			5:4	IO_SUPPLY_MODE	R/W	0x0	I/O supply mode 00: 1.8 V 11: 3.3 V If IO_SUPPLY_MODE_OV is 0, a read of this register returns the detected VDDIO voltage level.
			3:0	RESERVED	R/W	0x9	Reserved
Share	0x0E	GPIO_PIN_STS	7:4	RESERVED	R/W	0x0	Reserved
Share	0x0E	GPIO_PIN_STS	3:0	GPIO_STS	R	0x0	GPIO pin status This register reads the current values on each of the 4 GPIO pins. Bit 3 reads GPIO3 and bit 0 reads GPIO0.
Share	0x0F	GPIO_INPUT_CTL	7:4	RESERVED	R/W	0x7	Reserved
			3	GPIO3_INPUT_EN	R/W	0x1	GPIO3 input enable 0: Disabled 1: Enabled
			2	GPIO2_INPUT_EN	R/W	0x1	GPIO2 input enable 0: Disabled 1: Enabled
			1	GPIO1_INPUT_EN	R/W	0x1	GPIO1 input enable 0: Disabled 1: Enabled
			0	GPIO0_INPUT_EN	R/W	0x1	GPIO0 input enable 0: Disabled 1: Enabled
Share	0x10	GPIO0_PIN_CTL	7:5	GPIO0_OUT_SEL	R/W	0x0	GPIO0 output select Determines the output data for the selected source. If GPIO0_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000 : Received GPIO0 001 : Received GPIO1 010 : Received GPIO2 011 : Received GPIO3 100 : RX port lock indication 101 : RX port pass indication 110- 111 : Reserved If GPIO0_OUT_SRC is set to 100 (Device Status), the following selections apply: 000 : Value in GPIO0_OUT_VAL 001 : Logical OR of Lock indication from enabled RX ports 010 : Logical AND of Lock indication from enabled RX ports 011 : Logical AND of Pass indication from enabled RX ports 100 : FrameSync signal 101 - 111 : Reserved
			4:2	GPIO0_OUT_SRC	R/W	0x0	GPIO0 Output source select Selects output source for GPIO0 data: 000 : RX Port 0 001 : RX Port 1 01x : Reserved 100 : Device status 101 - 111 : Reserved
			1	GPIO0_OUT_VAL	R/W	0x0	GPIO0 output value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
			0	GPIO0_OUT_EN	R/W	0x0	GPIO0 Output Enable 0: Disabled 1: Enabled
Share	0x11	GPIO1_PIN_CTL	7:5	GPIO1_OUT_SEL	R/W	0x0	GPIO1 Output Select Determines the output data for the selected source. If GPIO1_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000 : Received GPIO0 001 : Received GPIO1 010 : Received GPIO2 011 : Received GPIO3 100 : RX Port Lock indication 101 : RX Port Pass indication 110- 111 : Reserved If GPIO1_OUT_SRC is set to 100 (Device Status), the following selections apply: 000 : Value in GPIO1_OUT_VAL 001 : Logical OR of Lock indication from enabled RX ports 010 : Logical AND of Lock indication from enabled RX ports 011 : Logical AND of Pass indication from enabled RX ports 100 : FrameSync signal 101 - 111 : Reserved
			4:2	GPIO1_OUT_SRC	R/W	0x0	GPIO1 Output Source Select Selects output source for GPIO1 data: 000 : RX port 0 001 : RX port 1 01x : Reserved 100 : Device status 101 - 111 : Reserved
			1	GPIO1_OUT_VAL	R/W	0x0	GPIO1 output value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
			0	GPIO1_OUT_EN	R/W	0x0	GPIO1 output enable 0: Disabled 1: Enabled
Share	0x12	GPIO2_PIN_CTL	7:5	GPIO2_OUT_SEL	R/W	0x0	GPIO2 output select Determines the output data for the selected source. If GPIO2_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000 : Received GPIO0 001 : Received GPIO1 010 : Received GPIO2 011 : Received GPIO3 100 : RX port lock indication 101 : RX port pass indication 110- 111 : Reserved If GPIO2_OUT_SRC is set to 100 (Device Status), the following selections apply: 000 : Value in GPIO2_OUT_VAL 001 : Logical OR of Lock indication from enabled RX ports 010 : Logical AND of Lock indication from enabled RX ports 011 : Logical AND of Pass indication from enabled RX ports 100 : FrameSync signal 101 - 111 : Reserved
			4:2	GPIO2_OUT_SRC	R/W	0x0	GPIO2 output source select Selects output source for GPIO2 data: 000 : RX port 0 001 : RX port 1 01x : Reserved 100 : Device status 101 - 111 : Reserved
			1	GPIO2_OUT_VAL	R/W	0x0	GPIO2 output value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
			0	GPIO2_OUT_EN	R/W	0x0	GPIO2 output enable 0: Disabled 1: Enabled
Share	0x13	GPIO3_PIN_CTL	7:5	GPIO3_OUT_SEL	R/W	0x0	GPIO3 output select Determines the output data for the selected source. If GPIO3_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000 : Received GPIO0 001 : Received GPIO1 010 : Received GPIO2 011 : Received GPIO3 100 : RX port lock indication 101 : RX port pass indication 110- 111 : Reserved If GPIO2_OUT_SRC is set to 100 (Device Status), the following selections apply: 000 : Value in GPIO3_OUT_VAL 001 : Logical OR of lock indication from enabled RX ports 010 : Logical AND of lock indication from enabled RX ports 011 : Logical AND of pass indication from enabled RX ports 100 : FrameSync signal 101 - 111 : Reserved
			4:2	GPIO3_OUT_SRC	R/W	0x0	GPIO3 output source select Selects output source for GPIO3 data: 000 : RX port 0 001 : RX port 1 01x : Reserved 100 : Device Status 101 - 111 : Reserved
			1	GPIO3_OUT_VAL	R/W	0x0	GPIO3 output value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
			0	GPIO3_OUT_EN	R/W	0x0	GPIO3 output enable 0: Disabled 1: Enabled
Share	0x14 - 0x17	RESERVED	7:0	RESERVED	R/W	0x0	Reserved
Share	0x18	FS_CTL	7:4	FS_MODE	R/W	0x0	FrameSync mode 0000: Internal generated FrameSync, use back-channel frame clock from port 0 0001: Internal generated FrameSync, use back-channel frame clock from port 1 0010 : Reserved 0011: Reserved 01xx: Internal generated FrameSync, use 25-MHz (typical) clock 1000: External FrameSync from GPIO0 1001: External FrameSync from GPIO1 1010: External FrameSync from GPIO2 1011: External FrameSync from GPIO3 1100 - 1111: Reserved
			3	FS_SINGLE	(R/W)/SC	0x0	Generate single FrameSync pulse When this bit is set, a single FrameSync pulse is generated. The system waits for the full duration of the desired pulse before generating another pulse. When using this feature, the FS_GEN_ENABLE bit remains set to 0. This bit is self-clearing and always returns to 0.
			2	FS_INIT_STATE	R/W	0x0	Initial State This register controls the initial state of the FrameSync signal. 0: FrameSync initial state is 0 1: FrameSync initial state is 1
			1	FS_GEN_MODE	R/W	0x0	FrameSync Generation Mode This control selects between Hi/Lo and 50/50 modes. In High/Lo mode, the FrameSync generator uses the FS_HIGH_TIME and FS_LOW_TIME register values to separately control the high and low periods for the generated FrameSync signal. In 50/50 mode, the FrameSync generator uses the values in the FS_HIGH_TIME_0, FS_LOW_TIME_1 and FS_LOW_TIME_0 registers as a 24-bit value for both the high and low periods of the generated FrameSync signal. 0: Hi/Lo 1: 50/50
			0	FS_GEN_ENABLE	R/W	0x0	FrameSync generation enable 0: Disabled 1: Enabled
Share	0x19	FS_HIGH_TIME_1	7:0	FRAMESYNC_HIGH_TIME_1	R/W	0x0	FrameSync high time bits 15:8 The value programmed to the FS_HIGH_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field results in a 1 cycle high pulse on the FrameSync signal.
Share	0x1A	FS_HIGH_TIME_0	7:0	FRAMESYNC_HIGH_TIME_0	R/W	0x0	FrameSync High Time bits 7:0 The value programmed to the FS_HIGH_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field results in a 1 cycle high pulse on the FrameSync signal.
Share	0x1B	FS_LOW_TIME_1	7:0	FRAMESYNC_LOW_TIME_1	R/W	0x0	FrameSync Low Time bits 15:8 The value programmed to the FS_LOW_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_LOW_TIME field results in a 1 cycle low pulse on the FrameSync signal.
Share	0x1C	FS_LOW_TIME_0	7:0	FRAMESYNC_LOW_TIME_0	R/W	0x0	FrameSync Low Time bits 7:0 The value programmed to the FS_LOW_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_LOW_TIME field results in a 1 cycle low pulse on the FrameSync signal.
Share	0x1D - 0x22	RESERVED	7:0	RESERVED	R	0x00	Reserved
Share	0x23	INTERRUPT_CTL	7	INT_EN	R/W	0x0	Global interrupt enable Enables interrupt on the interrupt signal to the controller.
			6:2	RESERVED	R/W	0x0	Reserved
			1	IE_RX1	R/W	0x0	RX port 1 Interrupt: Enable interrupt from receiver port 1.
			0	IE_RX0	R/W	0x0	RX Port 0 Interrupt: Enable interrupt from receiver port 0.
Share	0x24	INTERRUPT_STS	7	INT	R	0x0	Global Interrupt: Set if any enabled interrupt is indicated in the individual status bits in this register. The setting of this bit is not dependent on the INT_EN bit in the INTERRUPT_CTL register but does depend on the IE_xxx bits. For example, if IE_RX0 and IS_RX0 are both asserted, the INT bit is set to 1.
			6:2	RESERVED	R	0x0	Reserved
			1	IS_RX1	R	0x0	RX port 1 interrupt: An interrupt has occurred for receive port 1. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1 and RX_PORT_STS2.
			0	IS_RX0	R	0x0	RX Port 0 Interrupt: An interrupt has occurred for receive port 0. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1 and RX_PORT_STS2.
Share	0x25	FS_CONFIG	7	RESERVED	R/W	0x0	Reserved
			6	FS_POLARITY	R/W	0x0	Framesync Polarity Indicates active edge of FrameSync signal 0: Rising edge 1: Falling edge
			5:0	RESERVED	R/W	0x00	Reserved
Share	0x26 - 0x3A	RESERVED	7:0	RESERVED	R/W	0x00	Reserved
DVP	0x3B	DVP_CLK_CTL	7:1	RESERVED	R/W	0x00	Reserved
			4	ALLOW_PCLK	R/W	0x0	1: Allow monitoring CDR/SSCG clock on PCLK Pin without LOCK 0: Normal Mode"
			3:2	OSC_PCLK_SEL	R/W	0x0	Selects the frequency for the OSC clock out on PCLK when system is not locked and selected by OEN/OSS_SEL/OSC_PCLK_EN 00: 50M (+/- 30%) 01: 25M (+/- 30%) 10: 100M (+/- 30%) 11: 33.3M (+/- 30%)
			1	OSC_PCLK_EN	R/W	0x0	1: Output OSC clock when not LOCKED and OSS_SEL = 0 0: Only PCLK"
			0	RRFB	R/W	0x1	Pixel clock edge select (relative to the sink) 1: Parallel interface data is driven on the falling clock edge and sampled on the rising clock edge 0: Parallel interface data is driven on the rising clock edge and sampled on the falling clock edge
DVP	0x3C	DVP_FREQ_DET0	7:5	RESERVED	R/W	0x0	Reserved
DVP	0x3C	DVP_FREQ_DET0	4:0	FPD3_FREQ_LO_THR	R/W	0x14	Frequency low threshold Sets the low threshold for the CDR Clock frequency detect circuit in MHz. This value is used to determine if the clock frequency is too low for proper operation.
DVP	0x3D	DVP_FREQ_DET1	7:6	FPD3_FREQ_HYST	R/W	0x1	Frequency Hysteresis in units of MHz
DVP	0x3D	DVP_FREQ_DET1	5:0	FPD3_CLKIN_THR	R/W	0x2F	Frequency Threshold for dividing the CDR clock to send to the DVP PLL. Divider is set to 2 when CDR clock frequency is less than FPD3_CLKIN_THR, otherwise it is set to 3.
DVP	0x3E	DVP_SSCG_CTL	7:6	RESERVED	R	0x0	Reserved
			5	RESERVED	R/W	0x0	Reserved
			4	SSCG_ENABLE	R/W	0x0	Enable SSCG modulation 0 : SSCG modulation is disabled 1 : SSCG modulation is enabled Prior to enabling SSCG, the SSCG_MOD_RATE must be set. This requires a separate write to set the SSCG_MOD_RATE with SSCG disabled, then a write to set the SSCG_ENABLE with the same SSCG_MOD_RATE setting. In addition, when changing the SSCG_MOD_RATE, disable the SSCG first.
			3:1	RESERVED	R/W	0x0	Reserved
			0	SSCG_MOD_RATE	R/W	0x0	SSCG modulation frequency with its deviation 0: Reserved 1: frequency modulation PCLK/3168 ±1%
DVP	0x3F	DVP_FIFO_THOLD	7:0	DVP_FIFO_THRESHOLD	R/W	0x40	Starting threshold value for the DVP FIFO. This value sets the threshold for starting to pull data from the DVP FIFO. Once the amount of data in the FIFO reaches this threshold, data will begin transmission on the DVP interface. The threshold is in units of FPD-Link III clock cycles. The FIFO has a depth of 256, so setting to 0x40 will set the threshold at 1/4 of the FIFO.
Share	0x40	SFILTER_CTL	7	SFIL_ALWAYS_ON	R/W	0x0	Enable SFILTER Always Setting this bit allows SFILTER adaption at all times, including prior to lock. This bit overrides the SFIL_ADAPT_MODE setting. 1 : SFILTER adaption is always enabled 0 : SFILTER adaption only after locked (based on SFIL_ADAPT_MODE setting)
			6	SFIL_MEAS_ONLY	R/W	0x0	Enable SFILTER Measurement only Setting this bit allows SFILTER circuit to take mesaurements, but not update the SFILTER delay settings. 1 : Measurements only 0 : Allow adaption of SFILTER settings
			5:4	SFIL_THRESH_CTL	R/W	0x0	SFILTER Threshold Control Sets the threshold for incrementing or decrimenting the SFILTER. 00 : Use programmed threshold in SFIL_THRESHOLD register (default is 0) 01 : 60% ratio of early vs late 10 : 1/2 of previous opposite change (hysteresis) 11 : equal previous opposite change (hystersis)
			3:2	SFIL_SMPL_SIZE	R/W	0x0	SFILTER Sample Size Sets the sample size in FPD3 clocks for the SFILTER adaption routine. 00 : 256 samples 01 : 512 samples 10 : 1024 samples 11 : 2048 samples
			1	SFIL_ADAPT_MODE	R/W	0x0	SFILTER adapt mode This bit controls when SFILTER adaption is activated. If set to 0, adaption will begin as soon as the clock recovery circuit indicates the frequency is locked. If set to 1, adaption will wait until the AEQ adaption is complete. 1 : Wait for AEQ adaption complete 0 : Adapt after clock is locked
			0	SFILTER_EN	R/W	0x0	Enable Dynamic SFILTER adaption Setting this bit enables dynamic adaption of the SFILTER clock and data delays. 1 : Enable SFILTER adaption 0 : Disable SFILTER adaption
Share	0x41	SFILTER_CFG	7:4	SFILTER_MAX	R/W	0x8	SFILTER Maximum setting This field controls the maximum SFILTER setting. Allowed values are 0-14 with 7 being the mid point. These values are used for both AEQ adaption and dynamic SFILTER control. If AEQ_SFIL_ORDER is set in the AEQ_CTL register, the SFILTER_MAX value should not be set lower than 0x7
			3:0	SFILTER_MIN	R/W	0x6	SFILTER Minimum setting This field controls the minimum SFILTER setting. Allowed values are 0-14, where 7 is the mid point. These values are used for both AEQ adaption and dynamic SFILTER control. If AEQ_SFIL_ORDER is set in the AEQ_CTL register, the SFILTER_MIN value should not be set higher than 0x6
Share	0x42	AEQ_CTL	7	RESERVED	R	0x0	Reserved
			6:4	AEQ_ERR_CTL	R/W	0x7	AEQ Error Control Setting any of these bits will enable FPD3 error checking during the Adaptive Equalization process. Errors are accumulated over 1/2 of the period of the timer set by the ADAPTIVE_EQ_RELOCK_TIME filed in the AEQ_TEST register. If the number of errors is greater than the programmed threshold (AEQ_ERR_THOLD), the AEQ will attempt to increase the EQ setting. The errors may also be checked as part of EQ setting validation if AEQ_2STEP_EN is set. The following errors are checked based on this three bit field: [2] FPD3 clk1/clk0 errors [1] DCA sequence errors [0] Parity errors
			3	AEQ_SFIL_ORDER	R/W	0x0	AEQ SFILTER Adapt order This bit controls the order of adaption for SFILTER values during Adaptive Equalization. 0 : Default order, start at largest clock delay 1 : Start at midpoint, no additional clock or data delay
			2	AEQ_2STEP_EN	R/W	0x1	AEQ 2-step enable This bit enables a two-step operation as part of the Adaptive EQ algorithm. If disabled, the state machine will wait for a programmed period of time, then check status to determine if setting is valid. If enabled, the state machine will wait for 1/2 the programmed period, then check for errors over an additional 1/2 the programmed period. If errors occur during the 2nd step, the state machine will immediately move to the next setting. 0 : Wait for full programmed delay, then check instantaneous lock value 1 : Wait for 1/2 programmed time, then check for errors over 1/2 programmed time. The programmed time is controlled by the ADAPTIVE_EQ_RELOCK_TIME field in the AEQ_TEST register
			1	AEQ_OUTER_LOOP	R/W	0x0	AEQ outer loop control This bit controls whether the Equalizer or SFILTER adaption is the outer loop when the AEQ adaption includes SFILTER adaption. 0 : AEQ is inner loop, SFILTER is outer loop 1 : AEQ is outer loop, SFILTER is inner loop
			0	AEQ_SFILTER_EN	R/W	0x0	Enable SFILTER Adaption with AEQ Setting this bit allows SFILTER adaption as part of the Adaptive Equalizer algorithm.
Share	0x43	AEQ_ERR_THOLD	7:0	AEQ_ERR_THRESHOLD	R/W	0x1	AEQ Error Threshold This register controls the error threshold to determine when to re-adapt the EQ settings. This register should not be programmed to a value of 0.
Share	0x44 - 0x4B	RESERVED	7:0	RESERVED	R/W	0x00	Reserved
Share	0x4C	FPD3_PORT_SEL	7:6	PHYS_PORT_NUM	R	0x0	Physical port number This field provides the physical port connection when reading from a remote device via the bidirectional control channel. When accessed via local I2C interfaces, the value returned is always 0. When accessed via bidirectional control channel, the value returned is the port number of the receive port connection.
			5	RESERVED			Reserved
			4	RX_READ_PORT	R/W	0x0	Select RX port for register read This bit selects one of the two RX port register blocks for readback. This applies to all paged FPD3 receiver port registers. 0: Port 0 registers 1: Port 1 registers When accessed via local I2C interfaces, the default setting is 0. When accessed via bidirectional control channel, the default value is the port number of the receive port connection.
			3:2	RESERVED	R/W	0x0	Reserved
			1	RX_WRITE_PORT_1	R/W	0x0	Write Enable for RX port 1 registers This bit enables writes to RX port 1 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via bidirectional control channel, the default value is 1 if accessed over RX port 1.
			0	RX_WRITE_PORT_0	R/W	0x0	Write Enable for RX port 0 registers This bit enables writes to RX port 0 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bidirectional Control Channel, the default value is 1 if accessed over RX port 0.
RX	0x4D	RX_PORT_STS1	7	RESERVED	R	0x0	Reserved
			6	RX_PORT_NUM	R	0x0	RX port number This read-only field indicates the number of the currently selected RX read port.
			5	BCC_CRC_ERROR	R, LH	0x0	Bidirectional control channel CRC error detected This bit indicates a CRC error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read.
			4	LOCK_STS_CHG	R, LH	0x0	Lock status changed This bit is set if a change in receiver lock status has been detected since the last read of this register. Current lock status is available in the LOCK_STS bit of this register This bit is cleared on read.
			3	BCC_SEQ_ERROR	R, LH	0x0	Bidirectional control channel sequence error detected This bit indicates a sequence error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read.
			2	PARITY_ERROR	R, LH	0x0	FPD3 parity errors detected This flag is set when the number of parity errors detected is greater than the threshold programmed in the PAR_ERR_THOLD registers. 1: Number of FPD3 parity errors detected is greater than the threshold 0: Number of FPD3 parity errors is below the threshold. This bit is cleared when the RX_PAR_ERR_HI/LO registers are cleared.
			1	PORT_PASS	R	0x0	Receiver PASS indication This bit indicates the current status of the Receiver PASS indication. The requirements for setting the Receiver PASS indication are controlled by the PORT_PASS_CTL register. 1: Receive input has met PASS criteria 0: Receive input does not meet PASS criteria
			0	LOCK_STS	R	0x0	FPD-Link III receiver is locked to incoming data 1: Receiver is locked to incoming data 0: Receiver is not locked
RX	0x4E	RX_PORT_STS2	7:6	RESERVED	R	0x0	Reserved
			5	FPD3_ENCODE_ERROR	R, LH	0x0	FPD3 encoder error detected If set, this flag indicates an error in the FPD-Link III encoding has been detected by the FPD-Link III receiver. This bit is cleared on read.
			4:3	RESERVED	R	0x0	Reserved
			2	FREQ_STABLE	R	0x0	Frequency measurement stable
			1	NO_FPD3_CLK	R	0x0	No FPD-Link III input clock detected
			0	RESERVED	R	0x0	Reserved
RX	0x4F	RX_FREQ_HIGH	7:0	FREQ_CNT_HIGH	R	0x0	FPD Link-III frequency measurement high byte (MHz) The frequency counter reports the measured frequency for the FPD3 receiver. This portion of the field is the integer value in MHz. Frequency measurements scales with reference clock frequency.
RX	0x50	RX_FREQ_LOW	7:0	FREQ_CNT_LOW	R	0x0	FPD Link-III frequency measurement low byte (1/256 MHz) The Frequency counter reports the measured frequency for the FPD3 Receiver. This portion of the field is the fractional value in 1/256 MHz. Values scales with reference clock frequency.
RX	0x51	RESERVED	7:0	RESERVED	R	0x0	Reserved
RX	0x52	RESERVED	7:0	RESERVED	R	0x0	Reserved
RX	0x53	RESERVED	7:0	RESERVED	R	0x0	Reserved
RX	0x54	RESERVED	7:0	RESERVED	R	0x0	Reserved
RX	0x55	RX_PAR_ERR_HI	7:0	PAR ERROR BYTE 1	R	0x0	Number of FPD3 parity errors – 8 most significant bits. The parity error counter registers return the number of data parity errors that have been detected on the FPD3 Receiver data since the last detection of valid lock or last read of the RX_PAR_ERR_LO register. For accurate reading of the parity error count, disable the RX_PARITY_CHECKER_ENABLE bit in register 0x02 prior to reading the parity error count registers. This register is cleared upon reading the RX_PAR_ERR_LO register.
RX	0x56	RX_PAR_ERR_LO	7:0	PAR ERROR BYTE 0	R	0x0	Number of FPD3 parity errors – 8 least significant bits. The parity error counter registers return the number of data parity errors that have been detected on the FPD3 Receiver data since the last detection of valid lock or last read of the RX_PAR_ERR_LO register. For accurate reading of the parity error count, disable the RX_PARITY_CHECKER_ENABLE bit in register 0x02 prior to reading the parity error count registers. This register will be cleared on read.
RX	0x57	BIST_ERR_COUNT	7:0	BIST ERROR COUNT	R	0x0	BIST error count Returns BIST error count
RX	0x58	BCC_CONFIG	7	I2C PASS THROUGH ALL	R/W	0x0	I2C pass-through all transactions 0: Disabled 1: Enabled
			6	I2C PASS THROUGH	R/W	0x0	I2C pass-through to serializer if decode matches 0: Pass-through disabled 1: Pass-through enabled
			5	AUTO ACK ALL	R/W	0x0	Automatically acknowledge all I2C writes independent of the forward channel lock state or status of the remote acknowledge 1: Enable 0: Disable
			4	BACK CHANNEL ENABLE FOR CAMERA MODE	R/W	0x1	Back channel enable for camera mode (display mode BC is always enabled) 1: Enable 0: Disable
			3	BC CRC GENERATOR ENABLE	R/W	0x1	Back Channel CRC Generator Enable 0: Disable 1: Enable
			2	RESERVED	R/W	0x0	Reserved
			1:0	BC FREQ SELECT	(R/W)/S	0x0	Back channel frequency select 00: 2.5 Mbps (default) 01: 1.5625 Mbps 10 - 11 : Reserved Note that changing this setting results in some errors on the back channel for a short period of time. If set over the control channel, first program the deserializer to Auto-Ack operation to avoid a control channel timeout due to lack of response from the serializer.
RX	0x59	RESERVED	7:0	RESERVED	R/W	0x0	Reserved
RX	0x5A	RESERVED	7:0	RESERVED	R/W	0x0	Reserved
RX	0x5B	SER_ID	7:1	SER ID	R/W	0x00	Remote serializer ID This field is normally loaded automatically from the remote serializer.
			0	FREEZE DEVICE ID	R/W	0x0	Freeze serializer device ID Prevent auto-loading of the serializer device ID from the forward channel. The ID is frozen at the value written.
RX	0x5C	SER_ALIAS_ID	7:1	SER ALIAS ID	R/W	0x0	7-bit remote serializer alias ID Configures the decoder for detecting transactions designated for an I2C target device attached to the remote deserializer. The transaction will be remapped to the address specified in the target ID register. A value of 0 in this field disables access to the remote I2C target.
			0	SER AUTO ACK	R/W	0x0	Automatically acknowledge all I2C writes to the remote serializer independent of the forward channel lock state or status of the remote serializer acknowledge 1: Enable 0: Disable
RX	0x5D	targetID[0]	7:1	target ID0	R/W	0x0	7-bit remote target device ID 0 Configures the physical I2C address of the remote I2C target device attached to the remote serializer. If an I2C transaction is addressed to the target alias ID0, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x5E	targetID[1]	7:1	target ID1	R/W	0x0	7-bit remote target device ID 1 Configures the physical I2C address of the remote I2C target device attached to the remote Serializer. If an I2C transaction is addressed to the target alias ID1, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x5F	targetID[2]	7:1	target ID2	R/W	0x0	7-bit remote target device ID 2 Configures the physical I2C address of the remote I2C target device attached to the remote Serializer. If an I2C transaction is addressed to the target Alias ID2, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x60	targetID[3]	7:1	target ID3	R/W	0x0	7-bit remote target device ID 3 Configures the physical I2C address of the remote I2C target device attached to the remote serializer. If an I2C transaction is addressed to the target alias ID3, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x61	targetID[4]	7:1	target ID4	R/W	0x0	7-bit remote target device ID 4 Configures the physical I2C address of the remote I2C target device attached to the remote Serializer. If an I2C transaction is addressed to the target Alias ID4, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x62	targetID[5]	7:1	target ID5	R/W	0x0	7-bit remote target device ID 5 Configures the physical I2C address of the remote I2C target device attached to the remote serializer. If an I2C transaction is addressed to the target alias ID5, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x63	targetID[6]	7:1	target ID6	R/W	0x0	7-bit remote target device ID 6 Configures the physical I2C address of the remote I2C target device attached to the remote serializer. If an I2C transaction is addressed to the target alias ID6, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x64	targetID[7]	7:1	target ID7	R/W	0x0	7-bit remote target device ID 7 Configures the physical I2C address of the remote I2C target device attached to the remote serializer. If an I2C transaction is addressed to the target alias ID7, the transaction is remapped to this address before passing the transaction across the bidirectional control channel to the serializer.
			0	RESERVED	R	0x0	Reserved
RX	0x65	targetAlias[0]	7:1	target ALIAS ID0	R/W	0x0	7-bit remote target device alias ID 0 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID0 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 0	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 0 independent of the forward channel lock state or status of the remote serializer acknowledge. 1: Enable 0: Disable
RX	0x66	targetAlias[1]	7:1	target ALIAS ID1	R/W	0x0	7-bit remote target device alias ID 1 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID1 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 1	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 1 independent of the forward channel lock state or status of the remote serializer acknowledge 1: Enable 0: Disable
RX	0x67	targetAlias[2]	7:1	target ALIAS ID2	R/W	0x0	7-bit remote target device alias ID 2 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID2 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 2	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 2 independent of the forward channel lock state or status of the remote serializer acknowledge 1: Enable 0: Disable
RX	0x68	targetAlias[3]	7:1	target ALIAS ID3	R/W	0x0	7-bit remote target device alias ID 3 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID3 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 3	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 3 independent of the forward channel lock state or status of the remote serializer acknowledge. 1: Enable 0: Disable
RX	0x69	targetAlias[4]	7:1	target ALIAS ID4	R/W	0x0	7-bit remote target device alias ID 4 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID4 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 4	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 4 independent of the forward channel lock state or status of the remote serializer acknowledge. 1: Enable 0: Disable
RX	0x6A	targetAlias[5]	7:1	target ALIAS ID5	R/W	0x0	7-bit remote target device alias ID 5 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID5 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 5	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 5 independent of the forward channel lock state or status of the remote serializer acknowledge. 1: Enable 0: Disable
RX	0x6B	targetAlias[6]	7:1	target ALIAS ID6	R/W	0x0	7-bit remote target device alias ID 6 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID6 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 6	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 6 independent of the forward channel lock state or status of the remote serializer acknowledge. 1: Enable 0: Disable
RX	0x6C	targetAlias[7]	7:1	target ALIAS ID7	R/W	0x0	7-bit remote target device alias ID 7 Configures the decoder for detecting transactions designated for an I2C target device attached to the remote serializer. The transaction is remapped to the address specified in the target ID7 register. A value of 0 in this field disables access to the remote I2C target.
			0	target AUTO ACK 7	R/W	0x0	Automatically acknowledge all I2C writes to the remote target 7 independent of the forward channel lock state or status of the remote serializer acknowledge. 1: Enable 0: Disable
RX	0x6D	PORT_CONFIG	7:3	RESERVED	R/W	0x0F	Reserved
			2	COAX_MODE	(R/W)/S	0x0	Enable coax cable mode 0: Shielded twisted pair (STP) mode 1: Coax mode This bit is loaded from the MODE pin strap at power-up.
			1:0	FPD3_MODE	(R/W)/S	0x0	FPD3 input mode 00: Reserved 01: RAW12 LF mode 10: RAW12 HF mode 11: RAW10 mode This field is loaded from the MODE pin strap at power-up.
RX	0x6E	BC_GPIO_CTL0	7:4	BC_GPIO1_SEL	R/W	0x8	Back channel GPIO1 select: Determines the data sent on GPIO1 for the port back channel. 0000 : GPIO Pin 0 0001 : GPIO Pin 1 0010 : GPIO Pin 2 0011 : GPIO Pin 3 0100 - 0111 : Reserved 1000 : Constant value of 0 1001 : Constant value of 1 1010 : FrameSync signal 1011 - 1111 : Reserved
			3:0	BC_GPIO0_SEL	R/W	0x8	Back channel GPIO0 Select: Determines the data sent on GPIO0 for the port back channel. 0000 : GPIO Pin 0 0001 : GPIO Pin 1 0010 : GPIO Pin 2 0011 : GPIO Pin 3 0100 - 0111 : Reserved 1000 : Constant value of 0 1001 : Constant value of 1 1010 : FrameSync signal 1011 - 1111 : Reserved
RX	0x6F	BC_GPIO_CTL1	7:4	BC_GPIO3_SEL	R/W	0x8	Back channel GPIO3 select: Determines the data sent on GPIO3 for the port back channel. 0000 : GPIO Pin 0 0001 : GPIO Pin 1 0010 : GPIO Pin 2 0011 : GPIO Pin 3 0100 - 0111 : Reserved 1000 : Constant value of 0 1001 : Constant value of 1 1010 : FrameSync signal 1011 - 1111 : Reserved
			3:0	BC_GPIO2_SEL	R/W	0x8	Back channel GPIO2 select: Determines the data sent on GPIO2 for the port back channel. 0000 : GPIO Pin 0 0001 : GPIO Pin 1 0010 : GPIO Pin 2 0011 : GPIO Pin 3 0100 - 0111 : Reserved 1000 : Constant value of 0 1001 : Constant value of 1 1010 : FrameSync signal 1011 - 1111 : Reserved
RX	0x70 - 0x76	RESERVED	7:0	RESERVED	R/W	0x00	Reserved
RX	0x77	FREQ_DET_CTL	7:6	FREQ_HYST	R/W	0x3	Frequency detect hysteresis: The frequency detect hysteresis controls reporting of the FPD3 Clock frequency stability via the FREQ_STABLE status in the RX_PORT_STS2 register. The frequency is considered stable when the frequency remains within a range of +/- the FREQ_HYST value from the previous measurement. The FREQ_HYST setting is in MHz.
			5:4	FREQ_STABLE_THR	R/W	0x0	Frequency stability threshold: The frequency detect circuit can be used to detect a stable clock frequency. The stability threshold determines the amount of time required for the clock frequency to stay within the FREQ_HYST range to be considered stable: 00 : 40 µs 01 : 80 µs 10 : 320 µs 11 : 1.28 ms
			3:0	FREQ_LO_THR	R/W	0x5	Frequency low threshold: Sets the low threshold for the clock frequency detect circuit in MHz. If the input clock is below this threshold, the NO_FPD3_CLK status is set to 1.
RX	0x78	MAILBOX_1	7:0	MAILBOX_0	R/W	0x0	Mailbox register This register is an unused read/write register that can be used for any purpose such as passing messages between I2C controllers on opposite ends of the link.
RX	0x79	MAILBOX_2	7:0	MAILBOX_1	R/W	0x01	Mailbox register This register is an unused read/write register that can be used for any purpose such as passing messages between I2C controllers on opposite ends of the link.
RX	0x7A - 0x7F	RESERVED	7:0	RESERVED	R	0x0	Reserved
Share	0xB0	IND_ACC_CTL	7:6	RESERVED	R	0x0	Reserved
			5:2	IA_SEL	R/W	0x0	Indirect Access register select: Selects target for register access 0000 : Reserved 0001 : FPD3 RX Port 0 registers 0010 : FPD3 RX Port 1 registers 0011 : Reserved 0100 : Reserved 0101 : FPD3 RX Shared registers 0110 : Simultaneous write to FPD3 RX Port 0-1 registers 0111 : Reserved
			1	IA_AUTO_INC	R/W	0x0	Indirect access auto increment: Enables auto-increment mode. Upon completion of a read or write, the register address automatically increments by 1
			0	IA_READ	R/W	0x0	Indirect access read: Setting this allows generation of a read strobe to the selected register block upon setting of the IND_ACC_ADDR register. In auto-increment mode, read strobes is also asserted following a read of the IND_ACC_DATA register. This function is only required for blocks that need to pre-fetch register data.
Share	0xB1	IND_ACC_ADDR	7:0	IA_ADDR	R/W	0x0	Indirect access register offset: This register contains the 8-bit register offset for the indirect access.
Share	0xB2	IND_ACC_DATA	7:0	IA_DATA	R/W	0x0	Indirect access data: Writing this register causes an indirect write of the IND_ACC_DATA value to the selected analog block register. Reading this register returns the value of the selected block register
Share	0xB3	BIST Control	7:6	BIST_OUT_MODE	R/W	0x0	BIST output mode 00 : No toggling 01 : Alternating 1/0 toggling 1x : Toggle based on BIST data
			5:4	RESERVED	R/W	0x0	Reserved
			3	BIST PIN CONFIG	R/W	0x1	BIST Configured through pin 1: BIST configured through pin 0: BISTconfigured through bits 2:0 in this register
			2:1	BIST CLOCK SOURCE	R/W	0x0	BIST Clock Source This register field selects the BIST clock source at the Serializer. These register bits are automatically written to the CLOCK SOURCE bits (register offset 0x14) in the serializer after BIST is enabled. See the appropriate serializer register descriptions for details. Note: When connected to a DS90UB913A or DS90UB933, a setting of 0x3 may result in a clock frequency that is too slow for proper recovery.
			0	BIST_EN	R/W	0x0	BIST Control 1: Enabled 0: Disabled
Share	0xB8	MODE_IDX_STS	7	IDX_DONE	R	0x1	IDX Done: If set, indicates the IDX decode has completed and latched into the IDX status bits.
			6:4	IDX	R	0x0	IDX Decode 3-bit decode from IDX pin
			3	MODE_DONE	R	0x1	MODE Done: If set, indicates the MODE decode has completed and latched into the MODE status bits.
			2:0	MODE	R	0x0	MODE Decode 3-bit decode from MODE pin
Share	0xBE	GPIO_PD_CTL	7:3	RESERVED	R/W	0x0	Reserved
			2	GPIO2_PD_DIS	R/W	0x0	GPIO2 pulldown resistor disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1 : Disable GPIO pulldown resistor 0 : Enable GPIO pulldown resistor
			1	GPIO1_PD_DIS	R/W	0x0	GPIO1 pulldown resistor disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1 : Disable GPIO pulldown resistor 0 : Enable GPIO pulldown resistor
			0	GPIO0_PD_DIS	R/W	0x0	GPIO0 pulldown resistor disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1 : Disable GPIO pulldown resistor 0 : Enable GPIO pulldown resistor
RX	0xD0	PORT DEBUG	7:6	RESERVED	R/W	0x0	Reserved
			5	SER BIST ACT	R	0x0	Serializer BIST Active This register indicates whether the serializer is in BIST mode. 0: BIST mode not active 1: BIST mode active If the deserializer is not in BIST mode, this bit being 1 could indicate an error condition.
			4:2	RESERVED	R/W	0x0	Reserved
			1	FORCE BC ERRORS	R/W	0x0	This bit introduces continuous errors into the back channel frame.
			0	FORCE 1 BC ERROR	(R/W)/SC	0x0	This bit introduces typically one, worst case two, errors into the back channel frame. Self clearing bit.
RX	0xD2	RESERVED	7:0	ADAPTIVE_EQ_RELOCK_TIME	R/W	0x4	Time to wait for lock before incrementing the EQ to next setting 000 : 164 us 001 : 328 us 010 : 655 us 011 : 1.31 ms 100 : 2.62 ms 101 : 5.24 ms 110 : 10.5ms 111 : 21.0 ms
			4	AEQ_1ST_LOCK_MODE	R/W	0x0	AEQ First Lock Mode This register bit controls the Adaptive Equalizer algorithm operation at initial Receiver Lock. 0 : Initial AEQ lock may occur at any value 1 : Initial Receiver lock will restart AEQ at 0, providing a more deterministic initial AEQ value
			3	AEQ_RESTART	(R/W)/SC	0x0	Set high to restart AEQ adaptation from initial value. This bit is self clearing. Adaption will be restarted.
			2	SET_AEQ_FLOOR	R/W	0x0	AEQ adaptation starts from a pre-set floor value rather than from zero - good in long cable situations
			1:0	RESERVED	R	0x0	Reserved
RX	0xD3	AEQ_STATUS	7:6	RESERVED	R	0x0	Reserved
			5:3	EQ_STATUS_1	R	0x0	Adaptive EQ Status 1
			2:0	EQ_STATUS_2	R	0x0	Adaptive EQ Status 2
RX	0xD4	ADAPTIVE EQ BYPASS	7:5	EQ STAGE 1 SELECT VALUE	R/W	0x3	EQ select value [5:3] - Used if adaptive EQ is bypassed.
			4	AEQ_LOCK_MODE	R/W	0x0	Adaptive Equalizer lock mode When set to a 1, Receiver Lock status requires the Adaptive Equalizer to complete adaption. When set to a 0, Receiver Lock is based only on the Lock circuit itself. AEQ may not have stabilized.
			3:1	EQ STAGE 2 SELECT VALUE	R/W	0x0	EQ select value [2:0] - Used if adaptive EQ is bypassed.
			0	ADAPTIVE EQ BYPASS	R/W	0x0	1: Disable adaptive EQ 0: Enable adaptive EQ
RX	0xD5	AEQ_MIN_MAX	7:4	AEQ_MAX	R/W	0xF	Adaptive Equalizer Maximum value This register sets the maximum value for the Adaptive EQ algorithm.
			3:0	ADAPTIVE EQ FLOOR VALUE	R/W	0x8	When AEQ floor is enabled by register configuration {reg_35[5:4]} the starting setting is given by this register.
RX	0xD8	PORT_ICR_HI	7:3	Reserved	R	0x0	Reserved
			2	IE_FPD3_ENC_ERR	R/W	0x0	Interrupt on FPD-Link III receiver encoding error When enabled, an interrupt is generated on detection of an encoding error on the FPD-Link III interface for the receive port as reported in the FPD3_ENC_ERROR bit in the RX_PORT_STS2 register
			1	IE_BCC_SEQ_ERR	R/W	0x0	Interrupt on BCC SEQ sequence error When enabled, an interrupt is generated if a sequence error is detected for the bidirectional control channel forward channel receiver as reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register.
			0	IE_BCC_CRC_ERR	R/W	0x0	Interrupt on BCC CRC error detect When enabled, an interrupt is generated if a CRC error is detected on a bidirectional control channel frame received over the FPD-Link III forward channel as reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register.
RX	0xD9	PORT_ICR_LO	7:3	RESERVED	R/W	0x0	Reserved
			6	IE_LINE_LEN_CHG	R/W	0x0	Interrupt on Video Line length When enabled, an interrupt will be generated if the length of the video line changes. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register.
			5	IE_LINE_CNT_CHG	R/W	0x0	Interrupt on Video Line count When enabled, an interrupt will be generated if the number of video lines per frame changes. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register.
			4	IE_BUFFER_ERR	R/W	0x0	Interrupt on Receiver Buffer Error When enabled, an interrupt will be generated if the Receive Buffer overflow is detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register.
			3	RESERVED	R/W	0x0	Reserved
			2	IE_FPD3_PAR_ERR	R/W	0x0	Interrupt on FPD-Link III receiver parity error When enabled, an interrupt is generated on detection of parity errors on the FPD-Link III interface for the receive port. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register.
			1	IE_PORT_PASS	R/W	0x0	Interrupt on change in port PASS status When enabled, an interrupt is generated on a change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register.
			0	IE_LOCK_STS	R/W	0x0	Interrupt on change in lock status When enabled, an interrupt is generated on a change in lock status. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register.
RX	0xDA	PORT_ISR_HI	7:3	Reserved	R	0x0	Reserved
			2	IS_FPD3_ENC_ERR	R	0x0	FPD-Link III receiver encode error interrupt status An encoding error on the FPD-Link III interface for the receive port has been detected. Status is reported in the FPD3_ENC_ERROR bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register.
			1	IS_BCC_SEQ_ERR	R	0x0	BCC CRC sequence error interrupt status A sequence error has been detected for the bidirectional control channel forward channel receiver. Status is reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
			0	IS_BCC_CRC_ERR	R	0x0	BCC CRC error detect interrupt status A CRC error has been detected on a bidirectional control channel frame received over the FPD-Link III forward channel. Status is reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
RX	0xDB	PORT_ISR_LO	7:3	Reserved	R	0x0	Reserved
			6	IS_LINE_LEN_CHG	R	0x0	Video Line Length Interrupt Status A change in video line length has been detected. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register. This interrupt condition will be cleared by reading the RX_PORT_STS2 register.
			5	IS_LINE_CNT_CHG	R	0x0	Video Line Count Interrupt Status A change in number of video lines per frame has been detected. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register. This interrupt condition will be cleared by reading the RX_PORT_STS2 register.
			4	IS_BUFFER_ERR	R	0x0	Receiver Buffer Error Interrupt Status A Receive Buffer overflow has been detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register. This interrupt condition will be cleared by reading the RX_PORT_STS2 register.
			3	RESERVED	R	0x0	Reserved
			2	IS_FPD3_PAR_ERR	R	0x0	FPD-Link III receiver parity error interrupt status A parity error on the FPD-Link III interface for the receive port has been detected. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
			1	IS_PORT_PASS	R	0x0	Port valid interrupt status A change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
			0	IS_LOCK_STS	R	0x0	Lock interrupt status A change in lock status has been detected. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
Share	0xF0	FPD3_RX_ID0	7:0	FPD3_RX_ID0	R	0x5F	FPD3_RX_ID0: First byte ID code: ‘_’
Share	0xF1	FPD3_RX_ID1	7:0	FPD3_RX_ID1	R	0x55	FPD3_RX_ID1: 2nd byte of ID code: ‘U’
Share	0xF2	FPD3_RX_ID2	7:0	FPD3_RX_ID2	R	0x42	FPD3_RX_ID2: 3rd byte of ID code: ‘B’
Share	0xF3	FPD3_RX_ID3	7:0	FPD3_RX_ID3	R	0x39	FPD3_RX_ID3: 4th byte of ID code: ‘9’
Share	0xF4	FPD3_RX_ID4	7:0	FPD3_RX_ID4	R	0x33	FPD3_RX_ID4: 5th byte of ID code: '3'
Share	0xF5	FPD3_RX_ID5	7:0	FPD3_RX_ID5	R	0x34	FPD3_RX_ID5: 6th byte of ID code: '4'
Share	0xF8	I2C_RX0_ID	7:1	RX_PORT0_ID	R/W	0x00	7-bit Receive Port 0 I2C ID Configures the decoder for detecting transactions designated for Receiver port 0 registers. This provides a simpler method of accessing device registers specifically for port 0 without having to use the paging function to select the register page. A value of 0 in this field disables the Port0 decoder.
			0	RESERVED	R	0x0	Reserved
Share	0xF9	I2C_RX1_ID	7:1	RX_PORT1_ID	R/W	0x00	7-bit Receive Port 1 I2C ID Configures the decoder for detecting transactions designated for Receiver port 1 registers. This provides a simpler method of accessing device registers specifically for port 1 without having to use the paging function to select the register page. A value of 0 in this field disables the Port1 decoder.
			0	RESERVED	R	0x0	Reserved