SNLS605C July 2018 – April 2024 DS90UB935-Q1
PRODUCTION DATA
For a typical design application, use the parameters listed in Table 7-3.
DESIGN PARAMETER | PIN(S) | VALUE |
---|---|---|
V(VDD) | VDDD, VDDDRV, VDDPLL | 1.8V |
AC-Coupling Capacitor for Synchronous Modes, Coaxial Connection | DOUT+ | 33nF – 100nF (50 V / X7R / 0402) |
DOUT– | 15nF – 47nF (50 V / X7R / 0402) | |
AC-Coupling Capacitor for Synchronous Modes, STP Connection | DOUT+, DOUT– | 33 – 100nF (50V / X7R / 0402) |
AC-Coupling Capacitor for Non-Synchronous and DVP Backwards Compatible Modes, Coaxial Connection | DOUT+ | 100nF (50V / X7R / 0402) |
DOUT– | 47nF (50V / X7R / 0402) | |
AC-Coupling Capacitor for Non-Synchronous and DVP Backwards Compatible Modes, STP Connection | DOUT+, DOUT– | 100nF (50V / X7R / 0402) |
The SER/DES only supports AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in Figure 7-5 and Figure 7-6. For applications using single-ended 50Ω coaxial cable, terminate the unused data pins (DOUT+, DOUT–) with an AC-coupling capacitor and a 50Ω resistor.
For high-speed FPD–Link III transmissions, use the smallest available package for the AC-coupling capacitor to help minimize degradation of signal quality due to package parasitics.