SNLS605C July 2018 – April 2024 DS90UB935-Q1
PRODUCTION DATA
The DS90UB935-Q1 supports several clocking schemes, which are selected through the MODE pin. In the DS90UB935-Q1, the forward channel operates at a higher bandwidth than the requirement set by the video data transported, and the forward channel data rate is set by a reference clock. The clocking mode determines what the device uses as the reference clock, and the most common configuration is synchronous mode in which no local reference oscillator is required. See Table 6-8 for more information.
The default mode of the DS90UB935-Q1 is set by the application of a bias on the MODE pin during power up. More information on setting the operation modes can be found in Section 6.4.2.
MODE | DIVIDE | REFERENCE SOURCE | REF FREQUENCY (f) (MHz) | FC DATA RATE | CSI BANDWIDTH ≤ | CLK_OUT (3) |
---|---|---|---|---|---|---|
Synchronous | N/A | Back Channel(1) | 23 - 26 | f × 160 | 2.528 Gbps | f × 160 / HS_CLK_DIV × (M/N) |
Synchronous (Half-rate) | N/A | Back Channel(1) | 11.5 - 13 | f × 160 | 1.264Gbps | f × 160 / HS_CLK_DIV × (M/N) |
Non-Synchronous external clock | CLKIN_DIV = b000 | External Clock(2) | 25 - 52 | f × 80 | Lesser of f × 64 or 2.528 Gbps | f × 80 / HS_CLK_DIV × (M/N) |
CLKIN_DIV = b001 | External clock (2) | 50 - 104 | f × 40 | Lesser of f × 32 or 2.528 Gbps | f × 40 / HS_CLK_DIV × (M/N) | |
Non-Synchronous Internal Clock | OSCCLK_SEL = 1 | Internal Clock | 48.4 - 51 | f × 80 | 2.528 Gbps | N/A |
Non-Synchronous Internal Clock (Half-rate) | OSCCLK_SEL = 0 | Internal Clock | 24.2 - 25.5 | f × 80 | 1.264Gbps | N/A |
DVP External Clock Deserializer Mode: RAW10 |
N/A | External clock | 25 - 66.5 | f × 28 | f × 20 | f × 28 / HS_CLK_DIV × (M/N) |
DVP External Clock Deserializer Mode: RAW12 HF |
N/A | External clock | 25 - 70 | f × 28 | f × 18 | f × 28 / HS_CLK_DIV × (M/N) |