SNLS477D October 2014 – February 2022 DS90UB948-Q1
PRODUCTION DATA
In this configuration the PCLK rate embedded within 2-lane FPD-Link III frame can range from 50 MHz to 192 MHz, resulting in a link rate of 875 Mbps (35 bit × 25 MHz) to 3.36 Gbps (35 bit × 96 MHz). Each LVDS data lane will operate at a speed of 7 bits per LVDS clock cycle; resulting in a serial line rate of 350 Mbps to 1344 Mbps. CLK1 operates at the twice the rate as PCLK with a duty cycle ratio of 57:43.