SNLS477D October 2014 – February 2022 DS90UB948-Q1
PRODUCTION DATA
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is tri-state or LOW (depending on the value of the OUTPUT ENABLE setting). After the deserializer completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the LVCMOS and LVDS outputs. The state of the outputs is based on the OUTPUT ENABLE and OUTPUT SLEEP STATE SELECT register settings. See register 0x02 in Section 7.7.
INPUTS | OUTPUTS | |||||
---|---|---|---|---|---|---|
Serial INPUT | PDB | OUTPUT ENABLE
Reg 0x02 [7] |
OUTPUT SLEEP STATE
SELECT Reg 0x02 [4] |
LOCK | Data
GPIO / D_GPIO I2S |
D[7:0] / CLK[2:1] |
X | L | X | X | Z | Z | Z |
X | H | L | L | L | L | L |
X | H | L | H | L or H | Z | Z |
Static | H | H | L | L | L | L/OSC (Register EN) |
Static | H | H | H | L | L | L |
Active | H | H | L | L | L | L |
Active | H | H | H | H | Valid | Valid |