SNLS477D October   2014  – February 2022 DS90UB948-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  Timing Requirements for the Serial Control Bus
    8. 6.8  Switching Characteristics
    9. 6.9  Timing Diagrams and Test Circuits
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  Oscillator Output
      5. 7.3.5  Clock and Output Status
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Interrupt Pin — Functional Description and Usage (INTB_IN)
      9. 7.3.9  General-Purpose I/O (GPIO)
        1. 7.3.9.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 7.3.9.2 Back Channel Configuration
        3. 7.3.9.3 GPIO Register Configuration
      10. 7.3.10 SPI Communication
        1. 7.3.10.1 SPI Mode Configuration
        2. 7.3.10.2 Forward Channel SPI Operation
        3. 7.3.10.3 Reverse Channel SPI Operation
      11. 7.3.11 Backward Compatibility
      12. 7.3.12 Adaptive Equalizer
        1. 7.3.12.1 Transmission Distance
        2. 7.3.12.2 Adaptive Equalizer Algorithm
        3. 7.3.12.3 AEQ Settings
          1. 7.3.12.3.1 AEQ Start-Up and Initialization
          2. 7.3.12.3.2 AEQ Range
          3. 7.3.12.3.3 AEQ Timing
      13. 7.3.13 I2S Audio Interface
        1. 7.3.13.1 I2S Transport Modes
        2. 7.3.13.2 I2S Repeater
        3. 7.3.13.3 I2S Jitter Cleaning
        4. 7.3.13.4 MCLK
      14. 7.3.14 Repeater
        1. 7.3.14.1 Repeater Configuration
        2. 7.3.14.2 Repeater Connections
          1. 7.3.14.2.1 Repeater Fan-Out Electrical Requirements
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select MODE_SEL[1:0]
        1. 7.4.1.1 1-Lane FPD-Link III Input, Single Link OpenLDI Output
        2. 7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
        3. 7.4.1.3 2-Lane FPD-Link III Input, Dual Link OpenLDI Output
        4. 7.4.1.4 2-Lane FPD-Link III Input, Single Link OpenLDI Output
        5. 7.4.1.5 1-Lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
      2. 7.4.2 MODE_SEL[1:0]
        1. 7.4.2.1 Dual Swap
      3. 7.4.3 OpenLDI Output Frame and Color Bit Mapping Select
    5. 7.5 Image Enhancement Features
      1. 7.5.1 White Balance
      2. 7.5.2 LUT Contents
      3. 7.5.3 Enabling White Balance
        1. 7.5.3.1 LUT Programming Example
      4. 7.5.4 Adaptive Hi-FRC Dithering
    6. 7.6 Programming
      1. 7.6.1 Serial Control Bus
      2. 7.6.2 Multi-Controller Arbitration Support
      3. 7.6.3 I2C Restrictions on Multi-Controller Operation
      4. 7.6.4 Multi-Controller Access to Device Registers for Newer FPD-Link III Devices
      5. 7.6.5 Multi-Controller Access to Device Registers for Older FPD-Link III Devices
      6. 7.6.6 Restrictions on Control Channel Direction for Multi-Controller Operation
    7. 7.7 Register Maps
      1. 7.7.1 DS90UB948-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 FPD-Link III Interconnect Guidelines
        2. 8.2.2.2 AV Mute Prevention
        3. 8.2.2.3 Prevention of I2C Errors During Abrupt System Faults
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
    2. 9.2 Power Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Ground
    3. 10.3 Routing FPD-Link III Signal Traces
    4. 10.4 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN/FREQ.MINTYPMAXUNIT
LVDS DRIVER SWITCHING CHARACTERISTICS
tLVLHTLVDS low-to-high transition time20% to 80% transition, 5-pF load
See Figure 6-8		D0±, D1±, D2±, D3±, D4±, D5±, D6±, D7±, CLK1±, CLK2±0.150.25 ns
tLVHLTLVDS high-to-low transition time80% to 20% transition, 5-pF load
See Figure 6-8		0.150.25 ns
tBITTransmitter output bit widthT = 1 / OLDI clock frequency.
See Figure 6-10		1/7 × Tns
tPPOS0Transmitter output pulse positions normalized for Bit 01UI(1)
tPPOS1Transmitter output pulse positions normalized for Bit 12UI(1)
tPPOS2Transmitter output pulse positions normalized for Bit 23UI(1)
tPPOS3Transmitter output pulse positions normalized for Bit 34UI(1)
tPPOS4Transmitter output pulse positions normalized for Bit 45UI(1)
tPPOS5Transmitter output pulse positions normalized for Bit 56UI(1)
tPPOS6Transmitter output pulse positions normalized for Bit 67UI(1)
tPPOSTransmitter output pulse positions (Bit 6 - Bit 0) normalized< 0.1UI(1)
tCCSChannel-to-channel skew100ps
tJCCTransmitter jitter cycle-to-cycle2-lane FPD-Link III input, dual openLDI output0.16UI(1)
2-lane FPD-Link III input, single OpenLDI Output0.18UI(1)
1-lane FPD-Link III input, dual openLDI output0.04UI(1)
1-lane FPD-Link III input, single openLDI output0.04UI(1)
tPDDTransmitter power-down delaySee Figure 6-5100ns
tDDDeserializer propagation delayT = 1 / OLDI Clock frequency. See Figure 6-4147 × Tns
(1) UI - Unit Interval is equal to 1 / (7 × OLDI clock).