SNLS552E
September 2017 – April 2024
DS90UB953-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Recommended Timing for the Serial Control Bus
5.7
Timing Diagrams
5.8
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
CSI-2 Receiver
6.3.1.1
CSI-2 Receiver Operating Modes
6.3.1.2
CSI-2 Receiver High-Speed Mode
6.3.1.3
CSI-2 Protocol Layer
6.3.1.4
CSI-2 Short Packet
6.3.1.5
CSI-2 Long Packet
6.3.1.6
CSI-2 Errors and Detection
6.3.1.6.1
CSI-2 ECC Detection and Correction
6.3.1.6.2
CSI-2 Check Sum Detection
6.3.1.6.3
D-PHY Error Detection
6.3.1.6.4
CSI-2 Receiver Status
6.3.2
FPD-Link III Forward Channel Transmitter
6.3.2.1
Frame Format
6.3.3
FPD-Link III Back Channel Receiver
6.3.4
Serializer Status and Monitoring
6.3.4.1
Forward Channel Diagnostics
6.3.4.2
Back Channel Diagnostics
6.3.4.3
Voltage and Temperature Sensing
6.3.4.3.1
Programming Example
6.3.4.4
Built-In Self Test
6.3.5
FrameSync Operation
6.3.5.1
External FrameSync
6.3.5.2
Internally Generated FrameSync
6.3.6
GPIO Support
6.3.6.1
GPIO Status
6.3.6.2
GPIO Input Control
6.3.6.3
GPIO Output Control
6.3.6.4
Forward Channel GPIO
6.3.6.5
Back Channel GPIO
6.4
Device Functional Modes
6.4.1
Clocking Modes
6.4.1.1
Synchronous Mode
6.4.1.2
Non-Synchronous Clock Mode
6.4.1.3
Non-Synchronous Internal Mode
6.4.1.4
DVP Backwards Compatibility Mode
6.4.1.5
Configuring CLK_OUT
6.4.2
MODE
6.5
Programming
6.5.1
I2C Interface Configuration
6.5.1.1
CLK_OUT/IDX
6.5.1.1.1
IDX
6.5.2
I2C Interface Operation
6.5.3
I2C Timing
6.6
Pattern Generation
6.6.1
Reference Color Bar Pattern
6.6.2
Fixed Color Patterns
6.6.3
Packet Generator Programming
6.6.3.1
Determining Color Bar Size
6.6.4
Code Example for Pattern Generator
6.7
Register Maps
6.7.1
Main Registers
6.7.1.1
I2C Device ID Register
6.7.1.2
Reset
6.7.1.3
General Configuration
6.7.1.4
Forward Channel Mode Selection
6.7.1.5
BC_MODE_SELECT
6.7.1.6
PLL Clock Control
6.7.1.7
Clock Output Control 0
6.7.1.8
Clock Output Control 1
6.7.1.9
Back Channel Watchdog Control
6.7.1.10
I2C Control 1
6.7.1.11
I2C Control 2
6.7.1.12
SCL High Time
6.7.1.13
SCL Low Time
6.7.1.14
Local GPIO DATA
6.7.1.15
GPIO Input Control
6.7.1.16
DVP_CFG
6.7.1.17
DVP_DT
6.7.1.18
Force BIST Error
6.7.1.19
Remote BIST Control
6.7.1.20
Sensor Voltage Gain
6.7.1.21
Sensor Control 0
6.7.1.22
Sensor Control 1
6.7.1.23
Voltage Sensor 0 Thresholds
6.7.1.24
Voltage Sensor 1 Thresholds
6.7.1.25
Temperature Sensor Thresholds
6.7.1.26
CSI-2 Alarm Enable
6.7.1.27
Alarm Sense Enable
6.7.1.28
Back Channel Alarm Enable
6.7.1.29
CSI-2 Polarity Select
6.7.1.30
CSI-2 LP Mode Polarity
6.7.1.31
CSI-2 High-Speed RX Enable
6.7.1.32
CSI-2 Low Power Enable
6.7.1.33
CSI-2 Termination Enable
6.7.1.34
CSI-2 Packet Header Control
6.7.1.35
Back Channel Configuration
6.7.1.36
Datapath Control 1
6.7.1.37
Remote Partner Capabilities 1
6.7.1.38
Partner Deserializer ID
6.7.1.39
Target 0 ID
6.7.1.40
Target 1 ID
6.7.1.41
Target 2 ID
6.7.1.42
Target 3 ID
6.7.1.43
Target 4 ID
6.7.1.44
Target 5 ID
6.7.1.45
Target 6 ID
6.7.1.46
Target 7 ID
6.7.1.47
Target 0 Alias
6.7.1.48
Target 1 Alias
6.7.1.49
Target 2 Alias
6.7.1.50
Target 3 Alias
6.7.1.51
Target 4 Alias
6.7.1.52
Target 5 Alias
6.7.1.53
Target 6 Alias
6.7.1.54
Target 7 Alias
6.7.1.55
Back Channel Control
6.7.1.56
Revision ID
6.7.1.57
Device Status
6.7.1.58
General Status
6.7.1.59
GPIO Pin Status
6.7.1.60
BIST Error Count
6.7.1.61
CRC Error Count 1
6.7.1.62
CRC Error Count 2
6.7.1.63
Sensor Status
6.7.1.64
Sensor V0
6.7.1.65
Sensor V1
6.7.1.66
Sensor T
6.7.1.67
CSI-2 Error Count
6.7.1.68
CSI-2 Error Status
6.7.1.69
CSI-2 Errors Data Lanes 0 and 1
6.7.1.70
CSI-2 Errors Data Lanes 2 and 3
6.7.1.71
CSI-2 Errors Clock Lane
6.7.1.72
CSI-2 Packet Header Data
6.7.1.73
Packet Header Word Count 0
6.7.1.74
Packet Header Word Count 1
6.7.1.75
CSI-2 ECC
6.7.1.76
IND_ACC_CTL
6.7.1.77
IND_ACC_ADDR
6.7.1.78
IND_ACC_DATA
6.7.1.79
FPD3_TX_ID0
6.7.1.80
FPD3_TX_ID1
6.7.1.81
FPD3_TX_ID2
6.7.1.82
FPD3_TX_ID3
6.7.1.83
FPD3_TX_ID4
6.7.1.84
FPD3_TX_ID5
6.7.2
Indirect Access Registers
6.7.2.1
PATGEN Registers
6.7.2.2
Analog Registers
7
Application and Implementation
7.1
Application Information
7.1.1
Power-over-Coax
7.2
Typical Applications
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
CSI-2 Interface
7.2.2.2
FPD-Link III Input / Output
7.2.2.3
Internal Regulator Bypassing
7.2.2.4
Loop Filter Decoupling
7.2.3
Application Curve
7.3
Power Supply Recommendations
7.3.1
Power-Up Sequencing
7.3.1.1
System Initialization
7.3.1.1.1
Code Example for Temperature Ramp Initialization
7.3.2
Power Down (PDB)
7.4
Layout
7.4.1
Layout Guidelines
7.4.1.1
CSI-2 Guidelines
7.4.2
Layout Examples
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.2
Documentation Support
8.2.1
Related Documentation
8.3
Receiving Notification of Documentation Updates
8.4
Support Resources
8.5
Trademarks
8.6
Electrostatic Discharge Caution
8.7
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
RHB|32
QFND591
Orderable Information
snls552e_oa
6
Detailed Description