SNLS570C August 2017 – January 2023 DS90UB954-Q1
PRODUCTION DATA
Each DS90UB954-Q1 GPIO pin defaults to input mode at start-up. The deserializer can link GPIO pin input data on up to four available slots to send on the back channel per each remote serializer connection. Any of the seven GPIO pin data can be mapped to send over the available back channel slots for each FPD-Link III Rx port. The same GPIO on the deserializer pin can be mapped to multiple back channel GPIO signals. For each 50-Mbps back channel operation, the frame period is 600 ns (30 bits × 20 ns/bit). For 2.5-Mbps back channel operation, the frame period is 12 µs (30 bits × 400 ns/bit). As the back channel GPIOs are sampled and sent each back channel frame by the DS90UB954-Q1 deserializer, the latency and jitter timing are each on the order of one back channel frame. The back channel GPIO is effectively sampled at a rate of 1/30 of the back channel rate or 1.67 MHz at fBC = 50 Mbps. TI recommends that the input to back channel GPIO switching frequency is < 1/4 of the sampling rate or 416 kHz at fBC = 50 Mbps. For example, when operating in 4-Gbps synchronous mode with REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the data rate when linked over the back channel is shown in Table 7-10.
| BACK CHANNEL RATE (Mbps) | SAMPLING FREQUENCY (kHz) | MAXIMUM RECOMMENDED BACK CHANNEL GPIO FREQUENCY (kHz) | TYPICAL LATENCY (us) | TYPICAL JITTER (us) |
|---|---|---|---|---|
| 50 | 1670 | 416 | 1.5 | 0.7 |
| 10 | 334 | 83.5 | 3.2 | 3 |
| 2.5 | 83.5 | 20 | 12.2 | 12 |
In addition to sending GPIO from pins, an internally generated FrameSync or external FrameSync input signal may be mapped to any of the back channel GPIOs for synchronization of multiple sensors with extremely low skew. (see Section 7.4.27).
For each port, GPIO control is available through the BC_GPIO_CTL0 register 0x6E (see Table 7-120) and BC_GPIO_CTL1 register 0x6F (see Table 7-121).