SNLS589D August   2016  – September 2023 DS90UB960-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  CSI-2 Timing Specifications
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Receiver Port Control
        1. 7.4.5.1 Video Stream Forwarding
      6. 7.4.6  Input Jitter Tolerance
      7. 7.4.7  Adaptive Equalizer
        1. 7.4.7.1 Transmission Distance
        2. 7.4.7.2 Channel Requirements
        3. 7.4.7.3 Adaptive Equalizer Algorithm
        4. 7.4.7.4 AEQ Settings
          1. 7.4.7.4.1 AEQ Start-Up and Initialization
          2. 7.4.7.4.2 AEQ Range
          3. 7.4.7.4.3 AEQ Timing
          4. 7.4.7.4.4 AEQ Threshold
      8. 7.4.8  Channel Monitor Loop-Through Output Driver
        1. 7.4.8.1 Code Example for CMLOUT FPD3 RX Port 0:
      9. 7.4.9  RX Port Status
        1. 7.4.9.1 RX Parity Status
        2. 7.4.9.2 FPD-Link Decoder Status
        3. 7.4.9.3 RX Port Input Signal Detection
        4. 7.4.9.4 Line Counter
        5. 7.4.9.5 Line Length
      10. 7.4.10 Sensor Status
      11. 7.4.11 GPIO Support
        1. 7.4.11.1 GPIO Input Control and Status
        2. 7.4.11.2 GPIO Output Pin Control
        3. 7.4.11.3 Forward Channel GPIO
        4. 7.4.11.4 Back Channel GPIO
        5. 7.4.11.5 GPIO Pin Status
        6. 7.4.11.6 Other GPIO Pin Controls
      12. 7.4.12 RAW Mode LV / FV Controls
      13. 7.4.13 CSI-2 Protocol Layer
      14. 7.4.14 CSI-2 Short Packet
      15. 7.4.15 CSI-2 Long Packet
      16. 7.4.16 CSI-2 Data Identifier
      17. 7.4.17 Virtual Channel and Context
      18. 7.4.18 CSI-2 Mode Virtual Channel Mapping
        1. 7.4.18.1 Example 1
        2. 7.4.18.2 Example 2:
      19. 7.4.19 CSI-2 Transmitter Frequency
      20. 7.4.20 CSI-2 Output Bandwidth
        1. 7.4.20.1 CSI-2 Output Bandwidth Calculation Example
      21. 7.4.21 CSI-2 Transmitter Status
      22. 7.4.22 Video Buffers
      23. 7.4.23 CSI-2 Line Count and Line Length
      24. 7.4.24 FrameSync Operation
        1. 7.4.24.1 External FrameSync Control
        2. 7.4.24.2 Internally Generated FrameSync
          1. 7.4.24.2.1 Code Example for Internally Generated FrameSync
      25. 7.4.25 CSI-2 Forwarding
        1. 7.4.25.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 7.4.25.2 Synchronized CSI-2 Forwarding
        3. 7.4.25.3 Basic Synchronized CSI-2 Forwarding
          1. 7.4.25.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 7.4.25.4 Line-Interleaved CSI-2 Forwarding
          1. 7.4.25.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 7.4.25.5 Line-Concatenated CSI-2 Forwarding
          1. 7.4.25.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 7.4.25.6 CSI-2 Replicate Mode
        7. 7.4.25.7 CSI-2 Transmitter Output Control
        8. 7.4.25.8 Enabling and Disabling CSI-2 Transmitters
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus
      2. 7.5.2  Second I2C Port
      3. 7.5.3  I2C Target Operation
      4. 7.5.4  Remote Target Operation
      5. 7.5.5  Remote Target Addressing
      6. 7.5.6  Broadcast Write to Remote Devices
        1. 7.5.6.1 Code Example for Broadcast Write
      7. 7.5.7  I2C Controller Proxy
      8. 7.5.8  I2C Controller Proxy Timing
        1. 7.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 7.5.9  Interrupt Support
        1. 7.5.9.1 Code Example to Enable Interrupts
        2. 7.5.9.2 FPD-Link III Receive Port Interrupts
        3. 7.5.9.3 Interrupts on Forward Channel GPIO
        4. 7.5.9.4 Interrupts on Change in Sensor Status
        5. 7.5.9.5 Code Example to Readback Interrupts
        6. 7.5.9.6 CSI-2 Transmit Port Interrupts
      10. 7.5.10 Error Handling
        1. 7.5.10.1 Receive Frame Threshold
        2. 7.5.10.2 Port PASS Control
      11. 7.5.11 Timestamp – Video Skew Detection
      12. 7.5.12 Pattern Generation
        1. 7.5.12.1 Reference Color Bar Pattern
        2. 7.5.12.2 Fixed Color Patterns
        3. 7.5.12.3 Pattern Generator Programming
          1. 7.5.12.3.1 Determining Color Bar Size
        4. 7.5.12.4 Code Example for Pattern Generator
      13. 7.5.13 FPD-Link BIST Mode
        1. 7.5.13.1 BIST Operation
    6. 7.6 Register Maps
      1. 7.6.1 Main Registers
      2. 7.6.2 Indirect Access Registers
        1. 7.6.2.1 PATGEN_And_CSI-2 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 VDD Power Supply
      2. 8.4.2 Power-Up Sequencing
        1. 8.4.2.1 PDB Pin
        2. 8.4.2.2 System Initialization
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground
        2. 8.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 8.5.1.3 CSI-2 Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

7.4.11.4 Back Channel GPIO

Each DS90UB960-Q1 GPIO pin defaults to input mode at start-up. The deserializer can link GPIO pin input data on up to four available slots to send on the back channel per each remote serializer connection. Any of the 8 GPIO pin data can be mapped to send over the available back channel slots for each FPD-Link III Rx port. The same GPIO on the deserializer pin can be mapped to multiple back channel GPIO signals. For 50-Mbps back channel operation, the frame period is 600 ns (30 bits × 20 ns/bit). For 2.5-Mbps back channel operation, the frame period is 12 µs (30 bits × 400 ns/bit). As the back channel GPIOs are sampled and sent back by the DS90UB960-Q1 deserializer, the latency and jitter timing are on the order of one back channel frame. The back channel GPIO is effectively sampled at a rate of 1/30 of the back channel rate or 1.67 MHz at fBC = 50 Mbps. TI recommends that the input switching frequency for the back channel GPIO is < 1/4 of the sampling rate or 416 kHz at fBC = 50 Mbps. For example, when operating in 4-Gbps synchronous mode with REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the data rate when linked over the back channel is shown in Table 7-12.

Table 7-12 Back Channel GPIO Typical Timing
BACK CHANNEL RATE (Mbps)SAMPLING FREQUENCY (kHz)MAXIMUM RECOMMENDED BACK CHANNEL GPIO FREQUENCY (kHz)TYPICAL LATENCY (µs)TYPICAL JITTER (µs)
5016704161.50.7
1033483.53.23
2.583.52012.212

In addition to sending GPIO from pins, an internally generated FrameSync or external FrameSync input signal may be mapped to any of the back channel GPIOs for synchronization of multiple sensors with extremely low skew (see Section 7.4.24).

In addition to sending GPIO from pins, an internally generated FrameSync signal may be sent on any of the back channel GPIOs.

For each port, the following GPIO control is available through the BC_GPIO_CTL0 register 0x6E and BC_GPIO_CTL1 register 0x6F.