SNLS500A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.2 Layout Example

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the VQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder can flow unevenly through the DAP.

Example PCB layout is used to demonstrate both proper routing and proper solder techniques when designing in the Deserializer.

Figure 6-12 shows a PCB layout example are derived from the layout design of the DS90UB96X-Q1 Evaluation Board. The graphic and layout description are used to determine proper routing when designing the board. The high-speed FPD-Link III traces routed differentially up to the connector. A 100Ω differential characteristic impedance and 50Ω single-ended characteristic impedance traces are maintained as much as possible for both STP and coaxial applications. For the layout of a coaxial interconnects, coupled traces are recommended to be used with the RINx- termination near the connector.

GUID-20231206-SS0I-ZPNZ-X8RJ-VZK1BF93KPMD-low.svg Figure 6-12 DS90UB964 Example PCB Layout With Quad Mini-Fakra Connector
GUID-20231206-SS0I-1WMP-KQZJ-3DTVBXD1LNBC-low.svg Figure 6-13 Example Routing of FPD-Link III Traces to a Single Mini-Fakra Connector and PoC Components
GUID-20231206-SS0I-GNBC-FSWJ-7H8NMXFK266N-low.svg Figure 6-14 Example Routing of CSI-2 Traces