SNLS762 February   2024 DS90UB981-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Device and Documentation Support
    1. 4.1 Documentation Support
      1. 4.1.1 Related Documentation
    2. 4.2 Trademarks
    3. 4.3 Electrostatic Discharge Caution
    4. 4.4 Glossary
  6. 5Revision History
  7. 6Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

DS90UB981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UB981-Q1 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link. In ADAS compatible mode, the device is interoperable with 936, 95x, 96x & 97x deserializers supporting resolutions up to 8MP+/40fps.

Package Information
PART NUMBER PACKAGE (1) PACKAGE SIZE(2)
DS90UB981-Q1 RTD (VQFNP, 64) 9.00mm × 9.00mm
(1) For all available packages, see Section 6.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-20200910-CA0I-RHZH-CG1Z-HXQNGC9GMNSS-low.gif Simplified Application Diagram