SNLS337M October   2010  – August 2017 DS90UH926Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing Requirements for the Serial Control Bus
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization Gain
      5. 7.3.5  Common-Mode Filter Pin (CMF)
      6. 7.3.6  Video Control Signal Filter
      7. 7.3.7  EMI Reduction Features
        1. 7.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 7.3.8  Enhanced Progressive Turnon (EPTO)
      9. 7.3.9  LVCMOS VDDIO Option
      10. 7.3.10 Power Down (PDB)
      11. 7.3.11 Stop Stream Sleep
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Pixel Clock Edge Select (RFB)
      15. 7.3.15 Built In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward-Channel and Back-Channel Error Checking
      16. 7.3.16 Image Enhancement Features
        1. 7.3.16.1 White Balance
          1. 7.3.16.1.1 LUT Contents
          2. 7.3.16.1.2 Enabling White Balance
        2. 7.3.16.2 Adaptive HI-FRC Dithering
      17. 7.3.17 Internal Pattern Generation
      18. 7.3.18 I2S Receiving
        1. 7.3.18.1 I2S Jitter Cleaning
        2. 7.3.18.2 Secondary I2S Channel
          1. 7.3.18.2.1 MCLK
      19. 7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
      20. 7.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.20.1 GPIO[3:0] Enable Sequence
        2. 7.3.20.2 GPO_REG[8:4] Enable Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
      2. 7.4.2 Low Frequency Optimization (LFMODE)
      3. 7.4.3 Configuration Select (MODE_SEL)
      4. 7.4.4 HDCP Repeater
        1. 7.4.4.1 Repeater Connections
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 Qualified for Automotive Applications
    • Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 3B
    • Device CDM ESD Classification Level C6
    • Device MM ESD Classification Level M3
  • Integrated HDCP Cipher Engine With On-Chip Key Storage
  • Bidirectional Control Interface Channel Interface With I2C Compatible Serial Control Bus
  • Supports High-Definition (720p) Digital Video Format
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • 5- to 85-MHz PCLK Supported
  • Single 3.3-V Operation With 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
  • AC-Coupled STP Interconnect up to 10 Meters
  • Parallel LVCMOS Video Outputs
  • DC-Balanced and Scrambled Data With Embedded Clock
  • Adaptive Cable Equalization
  • Supports HDCP Repeater Application
  • Image Enhancement (White Balance and Dithering) and Internal Pattern Generation
  • EMI Minimization (SSCG and EPTO)
  • Low Power Modes Minimize Power Dissipation
  • Backward-Compatible Modes

2 Applications

  • Automotive Display for Navigation
  • Rear Seat Entertainment Systems

3 Description

The DS90UH926Q-Q1 deserializer, in conjunction with the DS90UH925Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.

An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features.

The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UH926Q-Q1 WQFN (60) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Diagram

DS90UH926Q-Q1 30136427.gif