SNLS337M October   2010  – August 2017 DS90UH926Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing Requirements for the Serial Control Bus
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization Gain
      5. 7.3.5  Common-Mode Filter Pin (CMF)
      6. 7.3.6  Video Control Signal Filter
      7. 7.3.7  EMI Reduction Features
        1. 7.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 7.3.8  Enhanced Progressive Turnon (EPTO)
      9. 7.3.9  LVCMOS VDDIO Option
      10. 7.3.10 Power Down (PDB)
      11. 7.3.11 Stop Stream Sleep
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Pixel Clock Edge Select (RFB)
      15. 7.3.15 Built In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward-Channel and Back-Channel Error Checking
      16. 7.3.16 Image Enhancement Features
        1. 7.3.16.1 White Balance
          1. 7.3.16.1.1 LUT Contents
          2. 7.3.16.1.2 Enabling White Balance
        2. 7.3.16.2 Adaptive HI-FRC Dithering
      17. 7.3.17 Internal Pattern Generation
      18. 7.3.18 I2S Receiving
        1. 7.3.18.1 I2S Jitter Cleaning
        2. 7.3.18.2 Secondary I2S Channel
          1. 7.3.18.2.1 MCLK
      19. 7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
      20. 7.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.20.1 GPIO[3:0] Enable Sequence
        2. 7.3.20.2 GPO_REG[8:4] Enable Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
      2. 7.4.2 Low Frequency Optimization (LFMODE)
      3. 7.4.3 Configuration Select (MODE_SEL)
      4. 7.4.4 HDCP Repeater
        1. 7.4.4.1 Repeater Connections
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)(3)
MIN MAX UNIT
Supply voltage – VDD33 −0.3 4 V
Supply voltage – VDDIO −0.3 4 V
LVCMOS I/O voltage −0.3 (VDDIO + 0.3) V
Deserializer input voltage −0.3 2.75 V
Junction temperature 150 °C
60-pin WQFN Package
Maximum power dissipation capacity at 25°C		 Derate above 25 °C 1/ RθJA °C/W
RθJA 31 °C/W
RθJC 2.4 °C/W
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549).

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±8000 V
Charged-device model (CDM), per AEC Q100-011 ±1250
Machine model, all pins ±250
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF		 Air Discharge (Pin 49 and 50) ±15000
Contact Discharge (Pin 49 and 50) ±8000
(ISO10605)
RD = 330 Ω, CS = 150 pF		 Air Discharge (Pin 49 and 50) ±15000
Contact Discharge (Pin 49 and 50) ±8000
(ISO10605)
RD = 2 kΩ, CS = 150 & 330 pF		 Air Discharge (Pin 49 and 50) ±15000
Contact Discharge (Pin 49 and 50) ±8000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage (VDD33) 3 3.3 3.6 V
LVCMOS supply voltage (VDDIO) Connect VDDIO to 3.3 V and use 3.3-V IOs 3 3.3 3.6 V
Connect VDDIO to 1.8 V and use 1.8-V IOs 1.71 1.8 1.89 V
Operating free air temperature (TA) −40 25 105 °C
PCLK frequency 5 85 MHz
Supply noise(1) 100 mVP-P
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

6.4 Thermal Information

THERMAL METRIC(1) DS90UH926Q-Q1 UNIT
NKB (WQFN)
60 PINS
RθJA Junction-to-ambient thermal resistance 26.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 8.1 °C/W
RθJB Junction-to-board thermal resistance 5.2 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 5.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
LVCMOS I/O DC SPECIFICATIONS
VIH High Level Input Voltage VDDIO = 3 to 3.6 V PDB 2 VDDIO V
VIL Low Level Input Voltage VDDIO = 3 to 3.6 V GND 0.8 V
IIN Input Current VIN = 0 V or VDDIO = 3 to 3.6 V −10 ±1 10 μA
VIH High Level Input Voltage VDDIO = 3 to 3.6 V OEN, OSS_SEL, BISTEN, BISTC / INTB_IN, GPIO[3:0] 2 VDDIO V
VDDIO = 1.71 to 1.89 V 0.65 ×
VDDIO 		VDDIO V
VIL Low Level Input Voltage VDDIO = 3 to 3.6 V GND 0.8 V
VDDIO = 1.71 to 1.89 V GND 0.35 ×
VDDIO 		V
IIN Input Current VIN = 0 V or VDDIO VDDIO = 3
to 3.6 V		 −10 ±1 10 μA
VDDIO = 1.7
to 1.89 V		 −10 ±1 10 μA
VOH High Level Output Voltage IOH = −4 mA VDDIO = 3 to 3.6 V R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, LOCK, PASS, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB, GPO_REG[8:4] 2.4 VDDIO V
VDDIO = 1.7
to 1.89 V		 VDDIO- 0.45 VDDIO V
VOL Low Level Output Voltage IOL = 4 mA VDDIO = 3 to 3.6 V GND 0.4 V
VDDIO = 1.7
to 1.89 V		 GND 0.35 V
IOS Output Short-Circuit Current VOUT = 0 V −60 mA
IOZ Tri-state Output Current VOUT = 0 V or VDDIO, PDB = L −10 10 μA
FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS
VTH Differential Threshold High Voltage VCM = 2.5 V
(Internal VBIAS)		 RIN+, RIN– 50 mV
VTL Differential Threshold Low Voltage −50 mV
VCM Differential Common-mode Voltage 1.8 V
RT Internal Termination Resistor - Differential 80 100 120 Ω
CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS
VODp-p Differential Output Voltage RL = 100 Ω CMLOUTP, CMLOUTN 360 mVp-p
SUPPLY CURRENT
IDD1 Supply Current
(includes load current)
f = 85 MHz		 CL = 12 pF,
Checker Board Pattern
Figure 1 		VDD33= 3.6 V VDD33 125 145 mA
IDDIO1 VDDIO= 3.6 V VDDIO 110 118 mA
VDDIO = 1.89 V 60 75
IDD2 Supply Current
(includes load current)
f = 85 MHz		 CL = 4 pF
Checker Board Pattern,
Figure 1 		VDD33 = 3.6 V VDD33 125 145 mA
IDDIO2 VDDIO = 3.6 V VDDIO 75 85 mA
VDDIO = 1.89 V 50 65
IDDS Supply Current Sleep Mode Without Input Serial Stream VDD33 = 3.6 V VDD33 90 115 mA
IDDIOS VDDIO = 3.6 V VDDIO 3 5 mA
VDDIO = 1.89 V 2 3
IDDZ Supply Current Power Down PDB = L, All LVCMOS inputs are floating or tied to GND VDD33 = 3.6 V VDD33 2 10 mA
IDDIOZ VDDIO = 3.6 V VDDIO 0.05 10 mA
VDDIO = 1.89 V 0.05 10
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
GPIO BIT RATE
BR Forward Channel Bit Rate See(4) (5) f = 5 – 85 MHz,
GPIO[3:0]		 0.25 × f Mbps
Back Channel Bit Rate > 50 > 75 kbps
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
EW Differential Output Eye Opening Width(6) RL = 100 Ω,
Jitter Freq > f / 40
Figure 2 (4)(5) 		CMLOUTP, CMLOUTN,
f = 85 MHz		 0.3 0.4 UI
EH Differential Output Eye Height 200 300 mV
BIST MODE
tPASS BIST PASS Valid Time
BISTEN = H
Figure 8 (4)(5) 		PASS 800 ns
SSCG MODE
fDEV Spread Spectrum Clocking Deviation Frequency SeeFigure 14, Table 1 and Table 2 (4)(5) f = 85 MHz,
SSCG = ON 		±0.5% ±2.5%
fMOD Spread Spectrum Clocking Modulation Frequency 8 100 kHz
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 × PCLK). The UI scales with PCLK frequency.

6.7 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Level SDA and SCL 0.7 × VDD33 VDD33 V
VIL Input Low Level Voltage SDA and SCL GND 0.3 × VDD33 V
VHY Input Hysteresis > 50 mV
VOL SDA, IOL = 1.25 mA 0 0.36 V
IIN SDA or SCL, VIN = VDD33 or GND –10 10 µA
tR SDA Rise Time – READ SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9 430 ns
tF SDA Fall Time – READ 20 ns
tSU;DAT Setup Time — READ SeeFigure 9 560 ns
tHD;DAT Holdup Time — READ SeeFigure 9 615 ns
tSP Input Filter 50 ns
CIN Input Capacitance SDA or SCL <5 pF
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

6.8 Recommended Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN NOM MAX UNIT
fSCL SCL Clock Frequency Standard Mode 0 100 kHz
Fast Mode 0 400 kHz
tLOW SCL Low Period Standard Mode 4.7 µs
Fast Mode 1.3 µs
tHIGH SCL High Period Standard Mode 4 µs
Fast Mode 0.6 µs
tHD;STA Hold time for a start or a repeated start condition
Figure 9 		Standard Mode 4 µs
Fast Mode 0.6 µs
tSU:STA Setup time for a start or a repeated start condition
Figure 9 		Standard Mode 4.7 µs
Fast Mode 0.6 µs
tHD;DAT Data Hold Time
Figure 9 		Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
tSU;DAT Data Setup Time
Figure 9 		Standard Mode 250 ns
Fast Mode 100 ns
tSU;STO Setup Time for STOP Condition, Figure 9 Standard Mode 4 µs
Fast Mode 0.6 µs
tBUF Bus Free Time
Between STOP and START,
Figure 9 		Standard Mode 4.7 µs
Fast Mode 1.3 µs
tr SCL and SDA Rise Time,
Figure 9 		Standard Mode 1000 ns
Fast Mode 300 ns
tf SCL and SDA Fall Time,
Figure 9 		Standard Mode 300 ns
Fast mode 300 ns

6.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
tRCP PCLK Output Period tRCP = tTCP PCLK 11.76 T 200 ns
tRDC PCLK Output Duty Cycle 45% 50% 55%
tCLH LVCMOS Low-to-High Transition Time
Figure 3 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, LOCK, PASS, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB 2 3 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 2 3 ns
tCHL LVCMOS High-to-Low Transition Time
Figure 3 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 2 3 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 2 3 ns
tROS Data Valid before PCLK – Setup Time
SSCG = OFF
Figure 6 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 2.2 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 2.2 ns
tROH Data Valid after PCLK – Hold Time
SSCG = OFF
Figure 6 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 3 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 3 ns
tXZR Active to OFF Delay
Figure 5(2)(3) 		OEN = L, OSS_SEL = H R[7:0], G[7:0], B[7:0] 10 ns
HS, VS, DE, PCLK, LOCK, PASS 15 ns
MCLK,I2S_CLK, I2S_WC, I2S_DA, I2S_DB 60 ns
tDDLT Lock Time
Figure 5(2)(3)(1)		 SSCG = OFF f = 5 – 85 MHz 5 40 ms
tDD Delay – Latency(2)(3) f = 5 – 85 MHz 147 × T ns
tDCCJ Cycle-to-Cycle Jitter(2)(3) SSCG = OFF f = 5 to <15 MHz 0.5 ns
f = 15 to 85 MHz 0.2 ns
I2S_CLK = 1 to 12.28 MHz ±2 ns
tONS Data Valid After OEN = H SetupTime
Figure 7(2)(3) 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, MCLK,I2S_CLK, I2S_WC, I2S_DA, I2S_DB 50 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 50 ns
tONH Data Tri-State After OEN = L SetupTime
Figure 7 (2) (3) 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 50 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 50 ns
tSES Data Tri-State after OSS_ SEL = H, Setup Time
Figure 7 (2) (3) 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 5 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 5 ns
tSEH Data to Low after OSS_SEL = L Setup Time
Figure 7 (2) (3) 		VDDIO = 1.71 to 1.89 V,
CL = 12 pF		 5 ns
VDDIO = 3 to 3.6 V,
CL = 12 pF		 5 ns
(1) tDDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
(2) Specification is ensured by characterization and is not tested in production.
(3) Specification is ensured by design and is not tested in production.

6.10 Timing Diagrams

DS90UH926Q-Q1 30136446.gif Figure 1. Checker Board Data Pattern
DS90UH926Q-Q1 30136474.gif Figure 2. CML Output Driver
DS90UH926Q-Q1 30136430.gif Figure 3. LVCMOS Transition Times
DS90UH926Q-Q1 30136447.gif Figure 4. Delay - Latency
DS90UH926Q-Q1 30136461.gif Figure 5. PLL Lock Times and PDB Tri-State Delay
DS90UH926Q-Q1 30136449.gif Figure 6. Output Data Valid (Setup and Hold) Times With SSCG = OFF
DS90UH926Q-Q1 30136450.gif Figure 7. Output State (Setup and Hold) Times
DS90UH926Q-Q1 30136451.gif Figure 8. BIST PASS Waveform
DS90UH926Q-Q1 30136436.gif Figure 9. Serial Control Bus Timing Diagram

6.11 Typical Characteristics

DS90UH926Q-Q1 wvfrm01_serial78_snls407.gif
NOTE: On the rising edge of each clock period, the CML driver outputs a low stop bit, high start bit, and 33 DC-scrambled data bits.
Figure 10. Serializer CML Driver Output
With 78-MHZ TX Pixel Clock
DS90UH926Q-Q1 wvfrm02_PCLK78_snls407.gif
Figure 11. Comparison of Deserializer LVCMOS RX PCLK Output Locked to a 78-MHz TX PCLK