SNLS478 Data sheet

SNLS478B NOVEMBER 2014 – May 2020 DS90UH940-Q1

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

NKD|64
- MPQS032B

Thermal pad, mechanical data (Package|Pins)

NKD|64
- QFND765

Orderable Information

7.4.3 CSI-2 Interface

The DS90UH940-Q1 (in default mode) takes RGB 24-bpp data bits defined in the serializer and directly maps the bits to the pixel color space in the data frame. The DS90UH940-Q1 follows the general frame format as described per the CSI-2 standard (Figure 30). Upon the end of the vertical sync pulse (VS), the DS90UH940-Q1 generates the frame end and frame start synchronization packets within the vertical blanking period. The timing of the Frame Start will not reflect the timing of the VS signal.

Upon the rising edge of the DE signal, each active line is output in a long data packet with the defined data format (Figure 13). At the end of each packet, the data lanes Dn± return to the LP-11 state, while the clock lane CLK± continue outputting the high-speed clock.

The DS90UH940-Q1 CSI-2 transmitter consists of a high-speed clock (CLK±) and data (Dn±) outputs based on a source synchronous interface. The half rate clock at CLK± is derived from the pixel clock sourced by the clock/data recovery circuit of the DS90UH940-Q1. The CSI-2 clock frequency is 3.5 times (four MIPI lanes) or seven times (two MIPI lanes) the recovered pixel clock frequency. The MIPI DPHY outputs either two or four high-speed data lanes (Dn±) according to the CSI-2 protocol. The data rate of each lane is seven times (four MIPI lanes) or 14 times (two MIPI lanes) the pixel clock. As an example in a 4-MIPI-lane configuration, at a pixel clock of 150 MHz, the CLK± runs at 525 MHz, and each data lane runs at 1050 Mbps.

The half-rate clock maintains a quadrature phase relationship to the data signals and allows receiver to sample data at the rising and falling edges of the clock (DDR). Figure 10 shows the timing relationship of the clock and data lines. The DS90UH940-Q1 supports continuous high-speed clock. High speed data are sent out at data lanes Dn± in bursts. In between data bursts, the data lanes return to low power (LP) states in according to protocol defined in D-PHY standard. The rising edge of the differential clock (CSI_CLK+ – CSI_CLK–) is sent during the first payload bit of a transmission burst in the data lanes.

Figure 30. CSI-2 General Frame Format