SNLS455A November   2014  – March 2019 DS90UH947-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Applications Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  OpenLDI Input Frame and Color Bit Mapping Select
      5. 7.3.5  Video Control Signals
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Serial Link Fault Detect
      8. 7.3.8  Interrupt Pin (INTB)
      9. 7.3.9  Remote Interrupt Pin (REM_INTB)
      10. 7.3.10 General-Purpose I/O
        1. 7.3.10.1 GPIO[3:0] Configuration
        2. 7.3.10.2 Back Channel Configuration
        3. 7.3.10.3 GPIO_REG[8:5] Configuration
      11. 7.3.11 SPI Communication
        1. 7.3.11.1 SPI Mode Configuration
        2. 7.3.11.2 Forward Channel SPI Operation
        3. 7.3.11.3 Reverse Channel SPI Operation
      12. 7.3.12 Backward Compatibility
      13. 7.3.13 Audio Modes
        1. 7.3.13.1 I2S Audio Interface
          1. 7.3.13.1.1 I2S Transport Modes
          2. 7.3.13.1.2 I2S Repeater
        2. 7.3.13.2 TDM Audio Interface
      14. 7.3.14 HDCP Repeater
        1. 7.3.14.1 HDCP
        2. 7.3.14.2 HDCP Repeater
          1. 7.3.14.2.1 Repeater Configuration
          2. 7.3.14.2.2 Repeater Connections
            1. 7.3.14.2.2.1 Repeater Fan-Out Electrical Requirements
            2. 7.3.14.2.2.2 HDCP I2S Audio Encryption
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
        1. 7.3.16.1 Pattern Options
        2. 7.3.16.2 Color Modes
        3. 7.3.16.3 Video Timing Modes
        4. 7.3.16.4 External Timing
        5. 7.3.16.5 Pattern Inversion
        6. 7.3.16.6 Auto Scrolling
        7. 7.3.16.7 Additional Features
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Modes of Operation
        1. 7.4.2.1 Single Link Operation
        2. 7.4.2.2 Dual Link Operation
        3. 7.4.2.3 Replicate Mode
        4. 7.4.2.4 Auto-Detection of FPD-Link III Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])

Configuration of the device may be done via the MODE_SEL[1:0] input pins, or via the configuration register bits. A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL[1:0] inputs. See Table 7 and Table 8. These values will be latched into register location during power-up:

Table 6. MODE_SEL[1:0] Settings

MODE SETTING FUNCTION
OLDI_DUAL: OpenLDI Interface 0 Single-pixel OpenLDI interface.
1 Dual-pixel OpenLDI interface.
REPEATER: Configure Repeater 0 Disable repeater mode.
1 Enable repeater mode.
MAPSEL: OpenLDI Bit Mapping 0 OpenLDI bit mapping.
1 SPWG bit mapping.
COAX: Cable Type 0 Enable FPD-Link III for twisted pair cabling.
1 Enable FPD-Link III for coaxial cabling.
DS90UH947-Q1 MODE_SEL.gifFigure 30. MODE_SEL[1:0] Connection Diagram

Table 7. Configuration Select (MODE_SEL0)

# RATIO
VR4/VDD18 		TARGET VR4
(V)		 SUGGESTED RESISTOR PULL-UP R3 kΩ (1% tol) SUGGESTED RESISTOR PULL-DOWN R4 kΩ (1% tol) OLDI_DUAL REPEATER
1 0 0 OPEN Any value less than 100 0 0
2 0.213 0.383 115 30.9 0 1
5 0.560 1.008 82.5 105 1 0
6 0.676 1.216 51.1 107 1 1

Table 8. Configuration Select (MODE_SEL1)

# RATIO
VR6/VDD18 		TARGET VR6
(V)		 SUGGESTED RESISTOR PULL-UP R5 kΩ (1% tol) SUGGESTED RESISTOR PULL-DOWN R6 kΩ (1% tol) MAPSEL COAX
1 0 0 OPEN Any value less than 100 0 0
2 0.213 0.383 115 30.9 0 0
3 0.328 0.591 107 52.3 0 1
4 0.444 0.799 113 90.9 0 1
5 0.560 1.008 82.5 105 1 0
6 0.676 1.216 51.1 107 1 0
7 0.792 1.425 30.9 118 1 1
8 1 1.8 Any value less than 100 OPEN 1 1

The strapped values can be viewed and/or modified in the following locations:

  • OLDI_DUAL : Latched into OLDI_IN_MODE (0x4F[6], inverted from strap value).
  • REPEATER : Latched into TX_RPTR (0xC2[5]).
  • MAPSEL : Latched into OLDI_MAPSEL (0x4F[7]).
  • COAX : Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]).