SNLS455A November   2014  – March 2019 DS90UH947-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Applications Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Back Channel Data Transfer
      3. 7.3.3  FPD-Link III Port Register Access
      4. 7.3.4  OpenLDI Input Frame and Color Bit Mapping Select
      5. 7.3.5  Video Control Signals
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Serial Link Fault Detect
      8. 7.3.8  Interrupt Pin (INTB)
      9. 7.3.9  Remote Interrupt Pin (REM_INTB)
      10. 7.3.10 General-Purpose I/O
        1. 7.3.10.1 GPIO[3:0] Configuration
        2. 7.3.10.2 Back Channel Configuration
        3. 7.3.10.3 GPIO_REG[8:5] Configuration
      11. 7.3.11 SPI Communication
        1. 7.3.11.1 SPI Mode Configuration
        2. 7.3.11.2 Forward Channel SPI Operation
        3. 7.3.11.3 Reverse Channel SPI Operation
      12. 7.3.12 Backward Compatibility
      13. 7.3.13 Audio Modes
        1. 7.3.13.1 I2S Audio Interface
          1. 7.3.13.1.1 I2S Transport Modes
          2. 7.3.13.1.2 I2S Repeater
        2. 7.3.13.2 TDM Audio Interface
      14. 7.3.14 HDCP Repeater
        1. 7.3.14.1 HDCP
        2. 7.3.14.2 HDCP Repeater
          1. 7.3.14.2.1 Repeater Configuration
          2. 7.3.14.2.2 Repeater Connections
            1. 7.3.14.2.2.1 Repeater Fan-Out Electrical Requirements
            2. 7.3.14.2.2.2 HDCP I2S Audio Encryption
      15. 7.3.15 Built-In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
        2. 7.3.15.2 Forward Channel and Back Channel Error Checking
      16. 7.3.16 Internal Pattern Generation
        1. 7.3.16.1 Pattern Options
        2. 7.3.16.2 Color Modes
        3. 7.3.16.3 Video Timing Modes
        4. 7.3.16.4 External Timing
        5. 7.3.16.5 Pattern Inversion
        6. 7.3.16.6 Auto Scrolling
        7. 7.3.16.7 Additional Features
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Modes of Operation
        1. 7.4.2.1 Single Link Operation
        2. 7.4.2.2 Dual Link Operation
        3. 7.4.2.3 Replicate Mode
        4. 7.4.2.4 Auto-Detection of FPD-Link III Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGC Package
64-Pin VQFN
Top View
DS90UH947-Q1 UH947B_Final_Pinout.gif

Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NO.
LVDS INPUT PINS
D7-
D6-
D5-
D4-
D3-
D2-
D1-
D0-		 7
5
3
1
59
55
53
51		 I, LVDS Inverting LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
D7+
D6+
D5+
D4+
D3+
D2+
D1+
D0+		 8
6
4
2
60
56
54
52		 I, LVDS True LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
CLK- 57 I, LVDS Inverting LVDS Clock Input
Each pair requires external 100-Ω differential termination for standard LVDS levels
CLK+ 58 I, LVDS True LVDS Clock Input
Each pair requires external 100-Ω differential termination for standard LVDS levels
LFOLDI 63 Analog OpenLDI Loop Filter
Connect to a 10-nF capacitor to GND
FPD-LINK III SERIAL PINS
DOUT0- 26 I/O FPD-Link III Inverting Output 0
The output must be coupled with a 33-nF capacitor
DOUT0+ 27 I/O FPD-Link III True Output 0
The output must be coupled with a 33-nF capacitor
DOUT1- 22 I/O FPD-Link III Inverting Output 1
The output must be coupled with a 33-nF capacitor
DOUT1+ 23 I/O FPD-Link III True Output 1
The output must be coupled with a 33-nF capacitor
LF 20 Analog FPD-Link III Loop Filter
Connect to a 10-nF capacitor to GND
CONTROL PINS
SDA 48 IO, Open-Drain I2C Data Input / Output Interface
Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
SCL 47 IO, Open-Drain I2C Clock Input / Output Interface
Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
I2CSEL 13 I, LVCMOS I2C Voltage Level Strap Option
Tie to VDDIO with a 10-kΩ resistor for 1.8-V I2C operation.
Leave floating for 3.3-V I2C operation.
This pin is read as an input at power up.
IDx 19 I, Analog I2C Address Select
External pullup to VDD18 is required under all conditions. DO NOT FLOAT.
Connect to external pullup and pulldown resistors to create a voltage divider.
MODE_SEL0 18 Analog Mode Select 0 Input. Refer to Table 7.
MODE_SEL1 32 Analog Mode Select 1 Input. Refer to Table 8.
PDB 31 I, LVCMOS Power-Down Mode Input Pin
INTB 49 O, Open-Drain Remote interrupt
INTB = H, Normal Operation
INTB = L, Interrupt Request
Recommended pullup: 4.7 kΩ to VDDIO. DO NOT FLOAT.
REM_INTB 10 O, LVCMOS LVCMOS Output
REM_INTB will directly mirror the status of the INTB_IN signal from the remote device. No separate serializer register read will be required to reset and change the status of this pin.
SPI PINS
MOSI 46 IO, LVCMOS SPI Master Output Slave Input
Only available in Dual Link Mode. Shared with D_GPIO0
MISO 45 IO, LVCMOS SPI Master Input Slave Output
Only available in Dual Link Mode. Shared with D_GPIO1
SPLK 44 IO, LVCMOS SPI Clock
Only available in Dual Link Mode. Shared with D_GPIO2
SS 43 IO, LVCMOS SPI Slave Select
Only available in Dual Link Mode. Shared with D_GPIO3
HIGH-SPEED GPIO PINS
D_GPIO0 46 IO, LVCMOS High-Speed GPIO0
Only available in Dual Link Mode. Shared with MOSI
D_GPIO1 45 IO, LVCMOS High-Speed GPIO1
Only available in Dual Link Mode. Shared with MISO
D_GPIO2 44 IO, LVCMOS High-Speed GPIO2
Only available in Dual Link Mode. Shared with SPLK
D_GPIO3 43 IO, LVCMOS High-Speed GPIO3
Only available in Dual Link Mode. Shared with SS
GPIO PINS
GPIO0 14 IO, LVCMOS General-Purpose Input/Output 0
GPIO1 15 IO, LVCMOS General-Purpose Input/Output 1
GPIO2 38 IO, LVCMOS General-Purpose Input/Output 2
Shared with I2S_DC
GPIO3 39 IO, LVCMOS General-Purpose Input/Output 3
Shared with I2S_DD
REGISTER-ONLY GPIO PINS
GPIO5_REG 37 IO, LVCMOS General-Purpose Input/Output 5
Local register control only. Shared with I2S_DB
GPIO6_REG 36 IO, LVCMOS General-Purpose Input/Output 6
Local register control only. Shared with I2S_DA
GPIO7_REG 34 IO, LVCMOS General-Purpose Input/Output 7
Local register control only. Shared with I2S_WC
GPIO8_REG 35 IO, LVCMOS General-Purpose Input/Output 8
Local register control only. Shared with I2S_CLK
SLAVE MODE LOCAL I2S CHANNEL PINS
I2S_WC 34 I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG
I2S_CLK 35 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG
I2S_DA 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG
I2S_DB 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG
I2S_DC 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2
I2S_DD 39 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3
POWER AND GROUND PINS
VDD18 24
62		 Power 1.8-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDOA11 50
64		 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDA11 12 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDHS11 21
28		 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDL11 9
42		 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDOP11 61 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDP11 17 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDS11 25 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.
VDDIO 16
33		 Power 1.8-V (±5%) LVCMOS I/O Power. Refer to Figure 35 or Figure 36.
GND Thermal Pad Ground.
OTHER PINS
RES0
RES2
RES3		 29
40
41		 Reserved. Tie to GND.
RES1 30 Reserved. Connect with 50Ω to GND.
NC 11 No connect. Leave floating Do not connect to VDD or GND.