SNLS231P September   2006  – August 2024 DS90UR124-Q1 , DS90UR241-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Serializer Input Timing Requirements for TCLK
    7. 5.7 Serializer Switching Characteristics
    8. 5.8 Deserializer Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Initialization and Locking Mechanism
      2. 6.3.2  Data Transfer
      3. 6.3.3  Resynchronization
      4. 6.3.4  Powerdown
      5. 6.3.5  Tri-State
      6. 6.3.6  Pre-Emphasis
      7. 6.3.7  AC-Coupling and Termination
        1. 6.3.7.1 Receiver Termination Option 1
        2. 6.3.7.2 Receiver Termination Option 2
        3. 6.3.7.3 Receiver Termination Option 3
      8. 6.3.8  Signal Quality Enhancers
      9. 6.3.9  @SPEED-BIST Test Feature
      10. 6.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Using the DS90UR241 and DS90UR124
      2. 7.1.2 Display Application
      3. 7.1.3 Typical Application Connection
    2. 7.2 Typical Applications
      1. 7.2.1 DS90UR241-Q1 Typical Application Connection
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Power Considerations
          2. 7.2.1.2.2 Noise Margin
          3. 7.2.1.2.3 Transmission Media
          4. 7.2.1.2.4 46
          5. 7.2.1.2.5 Live Link Insertion
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DS90UR124 Typical Application Connection
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout and Power System Considerations
        2. 7.4.1.2 LVDS Interconnect Guidelines
      2. 7.4.2 Layout Examples
  9. 7Device and Documentation Support
    1. 7.1 Device Support
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  10. 8Revision History
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over recommended operating supply and temperature ranges unless otherwise specified
PARAMETERTEST CONDITIONSPIN/FREQ.MINTYPMAXUNIT
LVCMOS DC SPECIFICATIONS
VIHHigh-Level Input VoltageTx: DIN[0:23], TCLK, TPWDNB, DEN, TRFB, RAOFF, VODSEL, RES0.
Rx: RPWDNB, RRFB, REN, PTOSEL, BISTEN, BISTM, SLEW, RES0.		2VDDV
VILLow-Level Input VoltageGND0.8V
VCLInput Clamp VoltageICL = −18mA–0.8–1.5V
IINInput CurrentVIN = 0V or 3.6VTx: DIN[0:23], TCLK, TPWDNB, DEN, TRFB, RAOFF, RES0.
Rx: RRFB, REN, PTOSEL, BISTEN, BISTM, SLEW, RES0.		–10±210µA
Rx: RPWDNB–20±520
VOHHigh-Level Output VoltageIOH = −2mA, SLEW = L
IOH = −4mA, SLEW = H		Rx: ROUT[0:23], RCLK, LOCK, PASS.2.33VDDV
VOLLow-Level Output VoltageIOL = 2mA, SLEW = L
IOL = 4mA, SLEW = H		GND0.330.5V
IOSOutput Short Circuit CurrentVOUT = 0V–40–70–110mA
IOZTri-state Output CurrentRPWDNB, REN = 0V,
VOUT = 0V or VDD		Rx: ROUT[0:23], RCLK, LOCK, PASS.–30±0.430µA
LVDS DC SPECIFICATIONS
VTHDifferential Threshold High VoltageVCM = 1.8VRx: RIN+, RIN−50mV
VTLDifferential Threshold Low Voltage–50mV
IINInput CurrentVIN = 2.4V, VDD = 3.6V±100±250µA
VIN = 0V, VDD = 3.6V±100±250
VODOutput Differential Voltage (DOUT+)–(DOUT−)RL = 100Ω, without pre-emphasis Figure 5-10VODSEL = LTx: DOUT+, DOUT−380500630mV
VODSEL = H5009001100
ΔVODOutput Differential Voltage UnbalanceRL = 100Ω,
without pre-emphasis		VODSEL = L150mV
VODSEL = H
VOSOffset VoltageRL = 100Ω,
without pre-emphasis		VODSEL = L11.251.50V
VODSEL = H
ΔVOSOffset Voltage UnbalanceRL = 100Ω,
without pre-emphasis		VODSEL = L350mV
VODSEL = H
IOSOutput Short Circuit CurrentDOUT = 0V, DIN = H,
TPWDNB = 2.4V		VODSEL = L–2–5–8mA
VODSEL = H–4.5–7.9–14
IOZTri-state Output CurrentTPWDNB = 0V,
DOUT = 0V OR VDD		–15±115µA
TPWDNB = 2.4V, DEN = 0V
DOUT = 0V OR VDD		–15±115
TPWDNB = 2.4V, DEN = 2.4V,
DOUT = 0V OR VDD
NO LOCK (NO TCLK)		–15±115
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDTSerializer
Total Supply Current
(includes load current)		RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = L		f = 43MHz,
checkerboard pattern Figure 5-1		6085mA
RL = 100Ω, PRE = 12kΩ,
RAOFF = H, VODSEL = L		6590
RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = H		f = 43MHz,
random pattern		6690
IDDTZSerializer
Supply Current Power-down		TPWDNB = 0V
(All other LVCMOS Inputs = 0V)		45µA
IDDRDeserializer
Total Supply Current
(includes load current)		CL = 4pF,
SLEW = H		f = 43MHz,
checkerboard pattern
LVCMOS Output Figure 5-2		85105mA
CL = 4pF,

SLEW = H		f = 43MHz,
random pattern
LVCMOS Output		80100
IDDRZDeserializer
Supply Current Power-down		RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
RIN+/RIN- = 0V)		50µA