After Serializer lock is established, the inputs DIN0–DIN23 are used to input data to the Serializer. Data is clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer outputs (DOUT±) are intended to drive point-to-point connections.

CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream (Figure 7-9). The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits in the serial stream. DCB functions as the DC Balance control bit and does not require any pre-coding of data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically performed within Serializer and Deserializer.

The chipset supports clock frequency ranges of 5MHz to 43MHz. Every clock cycle, 24 databits are sent along with 4 additional overhead control bits. Thus the line rate is 1.20Gbps maximum (140Mbps minimum). The link is extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to only 1 single LVDS pair providing a compression ratio of better then 25 to 1.

In the serialized data stream, data/embedded clock & control bits (24+4 bits) are transmitted from the Serializer data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is 43MHz, the serial rate is 43 × 28 = 1.20 Giga bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 43MHz, the payload data rate is 43 x 24 = 1.03Gbps. TCLK is provided by the data source and must be in the range of 5MHz to 43MHz nominal. The Serializer outputs (DOUT±) can drive a point-to-point connection as shown in Figure 7-8. The outputs transmit data when the enable pin (DEN) is high and TPWDNB is high. The DEN pin can be used to Tri-state the outputs when driven low.

When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high, data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the RRFB input. ROUT[23:0], LOCK and RCLK outputs will each drive a maximum of 4pF load with a 43MHz clock. REN controls Tri-state for ROUTn and the RCLK pin on the Deserializer.