SNLS313I September 2009 – October 2019 DS90UR905Q-Q1 , DS90UR906Q-Q1
PRODUCTION DATA.
The serializer converts a wide parallel input bus to a single serial output data stream, and also acts as a signal generator for the chipset Built-In Self Test (BIST) mode. The device can be configured via external pins or through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and also the FPD-Link II data coding that provides randomization, scrambling, and DC balancing of the video data. The serializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and also the system spread spectrum PCLK support. The serializer features power saving features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.