SNLS313I September   2009  – October  2019 DS90UR905Q-Q1 , DS90UR906Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Application Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     DS90UR905Q-Q1 Serializer Pin Functions
    2.     DS90UR906Q-Q1 Deserializer Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Serializer DC Electrical Characteristics
    6. 7.6  Deserializer DC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Timing Requirements for DC and AC Serial Control Bus
    9. 7.9  Timing Requirements for Serializer PCLK
    10. 7.10 Timing Requirements for Serial Control Bus
    11. 7.11 Switching Characteristics: Serializer
    12. 7.12 Switching Characteristics: Deserializer
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Data Transfer
      2. 8.3.2 Video Control Signal Filter — Serializer and Deserializer
      3. 8.3.3 Serializer Functional Description
        1. 8.3.3.1 EMI Reduction Features
          1. 8.3.3.1.1 Serializer Spread Spectrum Compatibility
        2. 8.3.3.2 Signal Quality Enhancers
          1. 8.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 8.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 8.3.3.3 Power-Saving Features
          1. 8.3.3.3.1 Serializer Power-down Feature (PDB)
          2. 8.3.3.3.2 Serializer Stop Clock Feature
          3. 8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
        4. 8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 8.3.3.5 Optional Serial Bus Control
        6. 8.3.3.6 Optional BIST Mode
      4. 8.3.4 Deserializer Functional Description
        1. 8.3.4.1  Signal Quality Enhancers
          1. 8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 8.3.4.2  EMI Reduction Features
          1. 8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
          2. 8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
          3. 8.3.4.2.3 Deserializer SSCG Generation — Optional
          4. 8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 8.3.4.3  Power-Saving Features
          1. 8.3.4.3.1 Deserializer Power-Down Feature (PDB)
          2. 8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
        4. 8.3.4.4  Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
        5. 8.3.4.5  Deserializer Oscillator Output (Optional)
        6. 8.3.4.6  Deserializer OP_LOW (Optional)
        7. 8.3.4.7  Deserializer Pixel Clock Edge Select (RFB)
        8. 8.3.4.8  Deserializer Control Signal Filter (Optional)
        9. 8.3.4.9  Deserializer Low Frequency Optimization (LF_Mode)
        10. 8.3.4.10 Deserializer Map Select
        11. 8.3.4.11 Deserializer Strap Input Pins
        12. 8.3.4.12 Optional Serial Bus Control
        13. 8.3.4.13 Optional BIST Mode
      5. 8.3.5 Built-In Self Test (BIST)
        1. 8.3.5.1 Sample BIST Sequence
        2. 8.3.5.2 BER Calculations
      6. 8.3.6 Optional Serial Bus Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Display Application
      2. 9.1.2 Live Link Insertion
      3. 9.1.3 Alternate Color / Data Mapping
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR905Q-Q1 Typical Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR906Q-Q1 Typical Connection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Transmission Media
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.12 Switching Characteristics: Deserializer

over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERS TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
tRCP PCLK output period tRCP = tTCP PCLK 15.38 T 200 ns
tRDC PCLK output duty cycle SSCG=OFF, 5–65 MHz PCLK 43% 50% 57%
SSCG=ON, 5–20 MHz 35% 59% 65%
SSCG=ON, 20–65 MHz 40% 53% 60%
tCLH LVCMOS
Low-to-high transition time, Figure 10 		VDDIO = 1.8 V, CL = 4 pF PCLK/RGB[7:0], HS, VS, DE 2.1 ns
VDDIO = 3.3 V, CL = 4 pF 2.0 ns
tCHL LVCMOS
High-to-low transition time, Figure 10 		VDDIO = 1.8 V
CL = 4 pF, OS_PCLK/DATA = L		 PCLK/RGB[7:0], HS, VS, DE 1.6 ns
VDDIO = 3.3 V
CL = 4 pF, OS_PCLK/DATA = H		 1.5 ns
tROS Data valid before PCLK – set-up time Figure 14 VDDIO = 1.71 to 1.89 V or 3.0 to 3.6 V
CL = 4pF (lumped load)		 RGB[7:0], HS, VS, DE 0.27 0.45 T
tROH Data valid after PCLK – hold time Figure 14 VDDIO = 1.71 to 1.89 V or 3.0 to 3.6 V
CL = 4pF (lumped load)		 RGB[7:0], HS, VS, DE 0.4 0.55 T
tDDLT(2) Deserializer lock time,
Figure 13 		SSC[3:0] = 0000 (OFF)(1) PCLK = 5 MHz 3 ms
SSC[3:0] = 0000 (OFF)(1) PCLK = 65 MHz 4 ms
SSC[3:0] = ON(1) PCLK = 5 MHz 30 ms
SSC[3:0] = ON(1) PCLK = 65 MHz 6 ms
tDD Deserializer delay – latency, Figure 11 SSC[3:0] = 0000 (OFF)(1) 139 × T 140 × T ns
tDPJ Deserializer period jitter SSC[3:0] = OFF(3)(5)(6) PCLK = 5 MHz 975 1700 ps
PCLK = 10 MHz 500 1000 ps
PCLK = 65 MHz 550 1250 ps
tDCCJ Deserializer cycle-to-cycle jitter SSC[3:0] = OFF(3)(4)(6) PCLK = 5 MHz 675 1150 ps
PCLK = 10 MHz 375 900 ps
PCLK = 65 MHz 500 1150 ps
tIJT Deserializer input jitter tolerance, Figure 16 EQ = OFF,
SSCG = OFF,
PCLK = 65 MHz		 for jitter freq < 2 MHz 0.9 UI
for jitter freq > 6 MHz 0.5 UI
BIST Mode
tPASS BIST PASS valid time,
BISTEN = 1, Figure 17 		1 10 µs
SSCG Mode
fDEV Spread spectrum clocking deviation frequency Under typical conditions PCLK = 5 to 65 MHz,
SSC[3:0] = ON		 ±0.5% ±2%
fMOD Spread spectrum clocking modulation frequency Under typical conditions PCLK = 5 to 65 MHz,
SSC[3:0] = ON		 8 100 kHz
(1) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(2) tDDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
(3) tDPJ is the maximum amount the period is allowed to deviate over many samples.
(4) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
(5) Specification is ensured by characterization and is not tested in production.
(6) Specification is ensured by design and is not tested in production.
DS90UR905Q-Q1 DS90UR906Q-Q1 30102046.gifFigure 1. Serializer Test Circuit
DS90UR905Q-Q1 DS90UR906Q-Q1 30102030.gifFigure 2. Serializer Output Waveforms
DS90UR905Q-Q1 DS90UR906Q-Q1 30102047.gifFigure 3. Serializer Output Transition Times
DS90UR905Q-Q1 DS90UR906Q-Q1 30102031.gifFigure 4. Serializer Input PCLK Waveform and Set and Hold Times
DS90UR905Q-Q1 DS90UR906Q-Q1 30102048.gifFigure 5. Serializer Lock Time
DS90UR905Q-Q1 DS90UR906Q-Q1 30102049.gifFigure 6. Serializer Disable Time
DS90UR905Q-Q1 DS90UR906Q-Q1 30102010.gifFigure 7. Serializer Latency Delay
DS90UR905Q-Q1 DS90UR906Q-Q1 30102050.gifFigure 8. Serializer Output Jitter
DS90UR905Q-Q1 DS90UR906Q-Q1 30102032.gifFigure 9. Checkerboard Data Pattern
DS90UR905Q-Q1 DS90UR906Q-Q1 30102005.gifFigure 10. Deserializer LVCMOS Transition Times
DS90UR905Q-Q1 DS90UR906Q-Q1 30102011.gifFigure 11. Deserializer Delay – Latency
DS90UR905Q-Q1 DS90UR906Q-Q1 30102013.gifFigure 12. Deserializer Disable Time (OSS_SEL = 0)
DS90UR905Q-Q1 DS90UR906Q-Q1 30102014.gifFigure 13. Deserializer PLL Lock Times and PDB TRI-STATE Delay
DS90UR905Q-Q1 DS90UR906Q-Q1 30102035.gifFigure 14. Deserializer Output Data Valid (Set-up and Hold) Times With SSCG = Off
DS90UR905Q-Q1 DS90UR906Q-Q1 30102034.gifFigure 15. Deserializer Output Data Valid (Set-up and Hold) Times With SSCG = On
DS90UR905Q-Q1 DS90UR906Q-Q1 30102016.gifFigure 16. Receiver Input Jitter Tolerance
DS90UR905Q-Q1 DS90UR906Q-Q1 30102052.gifFigure 17. BIST PASS Waveform
DS90UR905Q-Q1 DS90UR906Q-Q1 30102036.gifFigure 18. Serial Control Bus Timing Diagram