SNLS313I September   2009  – October  2019 DS90UR905Q-Q1 , DS90UR906Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Application Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     DS90UR905Q-Q1 Serializer Pin Functions
    2.     DS90UR906Q-Q1 Deserializer Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Serializer DC Electrical Characteristics
    6. 7.6  Deserializer DC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Timing Requirements for DC and AC Serial Control Bus
    9. 7.9  Timing Requirements for Serializer PCLK
    10. 7.10 Timing Requirements for Serial Control Bus
    11. 7.11 Switching Characteristics: Serializer
    12. 7.12 Switching Characteristics: Deserializer
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Data Transfer
      2. 8.3.2 Video Control Signal Filter — Serializer and Deserializer
      3. 8.3.3 Serializer Functional Description
        1. 8.3.3.1 EMI Reduction Features
          1. 8.3.3.1.1 Serializer Spread Spectrum Compatibility
        2. 8.3.3.2 Signal Quality Enhancers
          1. 8.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 8.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 8.3.3.3 Power-Saving Features
          1. 8.3.3.3.1 Serializer Power-down Feature (PDB)
          2. 8.3.3.3.2 Serializer Stop Clock Feature
          3. 8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
        4. 8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 8.3.3.5 Optional Serial Bus Control
        6. 8.3.3.6 Optional BIST Mode
      4. 8.3.4 Deserializer Functional Description
        1. 8.3.4.1  Signal Quality Enhancers
          1. 8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 8.3.4.2  EMI Reduction Features
          1. 8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
          2. 8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
          3. 8.3.4.2.3 Deserializer SSCG Generation — Optional
          4. 8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 8.3.4.3  Power-Saving Features
          1. 8.3.4.3.1 Deserializer Power-Down Feature (PDB)
          2. 8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
        4. 8.3.4.4  Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
        5. 8.3.4.5  Deserializer Oscillator Output (Optional)
        6. 8.3.4.6  Deserializer OP_LOW (Optional)
        7. 8.3.4.7  Deserializer Pixel Clock Edge Select (RFB)
        8. 8.3.4.8  Deserializer Control Signal Filter (Optional)
        9. 8.3.4.9  Deserializer Low Frequency Optimization (LF_Mode)
        10. 8.3.4.10 Deserializer Map Select
        11. 8.3.4.11 Deserializer Strap Input Pins
        12. 8.3.4.12 Optional Serial Bus Control
        13. 8.3.4.13 Optional BIST Mode
      5. 8.3.5 Built-In Self Test (BIST)
        1. 8.3.5.1 Sample BIST Sequence
        2. 8.3.5.2 BER Calculations
      6. 8.3.6 Optional Serial Bus Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Display Application
      2. 9.1.2 Live Link Insertion
      3. 9.1.3 Alternate Color / Data Mapping
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR905Q-Q1 Typical Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR906Q-Q1 Typical Connection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Transmission Media
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DS90UR90xQ-Q1 chipset translates a parallel RGB video interface into a high-speed serialized interface over a single pair. This serial bus scheme makes system design easy by eliminating skew problems between clock and data, reducing the number of connector pins, reducing the interconnect size, weight, cost, and easing overall PCB layout. In addition, internal DC-balanced decoding is used to support AC-coupled interconnects.

The DS90UR905Q-Q1 serializer embeds the clock, balances the data payload, and level shifts the signals to high-speed, low voltage differential signaling. Up to 24 inputs are serialized, along with the three video control signals. This supports full
24-bit color or 18-bit color and 6 general-purpose signals (for example, Audio I2S applications).

The DS90UR906Q-Q1 deserializer recovers the data (RGB) and control signals and extracts the clock from the serial stream. The DS90UR906Q-Q1 is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UR905Q-Q1 WQFN (48) 7.00 mm × 7.00 mm
DS90UR906Q-Q1 WQFN (60) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.