SNLS414E June   2012  – October 2016 DS90UR910-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC
    6. 6.6 Switching Characteristics: AC
    7. 6.7 Timing Requirements: Serial Control Bus (CCI and I2C)
    8. 6.8 Timing Requirements: DC and AC Serial Control Bus (CCI and I2C)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Receive Equalization
      2. 7.3.2 CSI-2 Interface
      3. 7.3.3 High-Speed Clock and Data
      4. 7.3.4 Data Frame RGB Mapping
      5. 7.3.5 Display Timing Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ultra-Low Power State
      2. 7.4.2 Non-Continuous or Continuous Clock
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus (CCI or I2C)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Transmission Media
      2. 10.1.2 PCB Layout and Power System Considerations
      3. 10.1.3 CSI-2 Guidelines
      4. 10.1.4 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UR910-Q1 device recovers data from the FPD-Link II serial bit stream and converts into CSI-2. The recovered data is packetized and serialized over two data lanes strobed by a half-rate serial clock compliant with the MIPI DPHY and CSI-2 specifications, each running up to 900 Mbps. The FPD-Link II receiver supports pixel clocks of up to 75 MHz. The CSI-2 output serial bus greatly reduces the interconnect and signal count to a graphic processing unit (GPU) and eases system designs for video streams from multiple automotive driver assist cameras.

8.2 Typical Application

DS90UR910-Q1 30188444.gif Figure 16. DS90UR910-Q1 Typical Connection Diagram — Pin Control

8.2.1 Design Requirements

For this typical design application, Table 8 lists the input parameters.

Table 8. Design Parameters

PARAMETER VALUE
VDDIO 1.8 V or 3.3 V
VDDL, VDDA, VDDP, VDDCSI 1.8 V
AC-coupling capacitor for RIN0± and RIN1± 100 nF

8.2.2 Detailed Design Procedure

Figure 16 shows a typical application of the DS90UR910-Q1 in Pin control mode for a 24-bit Color Display Application. The LVDS signals require 100-nF AC-coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor must be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN pins. The interface to the host is with 1.8-V LVCMOS levels, thus the VDDIO pin is connected also to the 1.8-V rail. The optional I2C or CCI is connected to the Host bus in this example, thus the SCL and SDA pins are using pullup resistors R to VDDIO. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.

The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link II signal path as illustrated in Figure 17.

DS90UR910-Q1 STP_AC_COUPLE.gif Figure 17. AC-Coupled Connection

For high-speed FPD-Link II transmissions, the smallest available package must be used for the AC coupling capacitor. This helps minimize degradation of signal quality due to package parasitics. The inputs and outputs require 100-nF AC-coupling capacitors to the line.

8.2.3 Application Curves

Figure 18 corresponds to 49-MHz PCLK UNH pattern.

DS90UR910-Q1 910Eye.gif Figure 18. Loop-Through CML Output at 1.372-Gbps Serial Line Rate