SNLS414E June   2012  – October 2016 DS90UR910-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC
    6. 6.6 Switching Characteristics: AC
    7. 6.7 Timing Requirements: Serial Control Bus (CCI and I2C)
    8. 6.8 Timing Requirements: DC and AC Serial Control Bus (CCI and I2C)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Receive Equalization
      2. 7.3.2 CSI-2 Interface
      3. 7.3.3 High-Speed Clock and Data
      4. 7.3.4 Data Frame RGB Mapping
      5. 7.3.5 Display Timing Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ultra-Low Power State
      2. 7.4.2 Non-Continuous or Continuous Clock
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus (CCI or I2C)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Transmission Media
      2. 10.1.2 PCB Layout and Power System Considerations
      3. 10.1.3 CSI-2 Guidelines
      4. 10.1.4 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RTA Package
40-Pin WQFN
Top View

Pin Functions

PIN TYPE(2) DESCRIPTION
NAME(1) NO.
FPD-LINK II SERIAL INTERFACE
RIN+ 33 I CML, inverting and noninverting differential inputs. The inputs must be AC-coupled with a 100-nF capacitor.
RIN– 34 I CML, inverting and noninverting differential inputs. The inputs must be AC-coupled with a 100-nF capacitor.
CMF 35 I Analog, common mode filter pin for the differential inputs. CMP is the virtual ground of the differential input stage. A bypass capacitor is connected from CMP to ground to increase the receiver’s common mode noise immunity. TI recommends a 4.7-µF ceramic capacitor.
CMLOUT+ 37 O CML, inverting and noninverting differential outputs. Single 100-Ω (1%) termination resistor must be placed across the CMLOUT± pins. Optional loop-through output to monitor post equalizer and requires use of the Serial Control Bus to enable.
CMLOUT– 38 O CML, inverting and noninverting differential outputs. Single 100-Ω (1%) termination resistor must be placed across the CMLOUT± pins. Optional loop-through output to monitor post equalizer and requires use of the Serial Control Bus to enable.
MIPI INTERFACE
DATA1+ 19 O DPHY, inverting and noninverting data output of DPHY Lane 1.
DATA1– 18 O DPHY, inverting and noninverting data output of DPHY Lane 1.
DATA0+ 16 O DPHY, inverting and noninverting data output of DPHY Lane 0.
DATA0– 15 O DPHY, inverting and noninverting data output of DPHY Lane 0.
CLK+ 13 O DPHY, inverting and noninverting half-rate DPHY clock lane.
CLK– 12 O DPHY, inverting and noninverting half-rate DPHY clock lane.
CONTROL AND CONFIGURATION
PDB 30 I LVCMOS with pulldown, power down mode input;
PDB = 1, Device is enabled (normal operation),
PDB = 0, Device is in power-down,
When the device is in the power-down, outputs are TRI-STATE, control registers are RESET.
CONFIG[1:0] 10, 11 I LVCMOS with pulldown, operating mode select;
CONFIG[1:0] selects compatibility to FPD-Link II serializers. See Table 1.
EQ[3:1] 1, 2, 3 I LVCMOS with pulldown, receive equalization control;
EQ[3:1] provides 8 combinations of the receive equalization gain settings. See Table 2. EQ[3:1] optimizes the input equalizer’s ability to reduce inter-symbol interference from the loss characteristics of different cable lengths.
BISTEN 29 I LVCMOS with pulldown, BIST enable input;
BISTEN = 1, BIST is enabled,
BISTEN = 0, BIST is disabled.
LOCK 24 O LVCMOS, LOCK status output;
LOCK = 1, PLL acquired lock to the reference clock input; DPHY outputs are active
LOCK = 0, PLL is unlocked
PASS 25 O LVCMOS, normal mode status output pin (BISTEN = 0);
PASS = 1: No fault detected on input display timing,
PASS = 0: Indicates an error condition or corruption in display timing. Fault condition occurs if:
  1) DE length value mismatch measured once in succession,
  2) VSync length value mismatch measured twice in succession,
BIST mode status output pin (BISTEN = 1);
PASS = 1: No error detected,
PASS = 0: Error detected.
CCI AND I2C SERIAL CONTROL BUS
SCL 6 I LVCMOS open drain, serial control bus clock input,
SCL requires an external pullup resistor to VDDIO.
SDA 5 I/O LVCMOS open drain, serial control bus data input and output,
SDA requires an external pullup resistor to VDDIO.
ID[1:0] 8, 9 I LVCMOS with pulldown, serial control bus device ID address select,
see Table 6.
RESERVED PINS
GPIO 21 I/O General purpose I/O;
Pin must be left floating during initial power-up.
RES 28 I LVCMOS with pulldown, reserved pin (must tie low)
POWER AND GROUND
VDDL 7, 26 P Power to logic circuitry, 1.8 V ±5%
VDDA 31, 39 P Power to analog circuitry, 1.8 V ±5%
VDDP 40 P Power to PLL, 1.8 V ±5%
VDDCSI 20 P Power to DPHY CSI-2 drivers, 1.8 V ±5%
VDDIO 23 P Power to LVCMOS I/O circuitry, 1.8 V ±5% or 3.3 V ±10% (VDDIO)
GND 4, 14, 17, 22, 27, 32, 36 G Ground return
GND DAP G DAP is the metal contact at the bottom side, located at the center of the WQFN package. It must be connected to the GND plane with multiple via to lower the ground impedance and improve the thermal performance of the package. Connected to the ground plane (GND) with at least 9 vias.
(1) 1 = HIGH, 0 = LOW
(2) G = Ground, I = Input, O = Output, P = Power