SNLS325D May   2010  – December 2016 DS92LV0421 , DS92LV0422

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Serializer DC
    6. 6.6  Electrical Characteristics: Deserializer DC
    7. 6.7  Electrical Characteristics: DC and AC Serial Control Bus
    8. 6.8  Timing Requirements: Serial Control Bus
    9. 6.9  Switching Characteristics: Serializer
    10. 6.10 Switching Characteristics: Deserializer
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Parallel LVDS Data Transfer (Color Bit Mapping Select)
      2. 7.3.2 Serial Data Transfer
      3. 7.3.3 Video Control Signal Filter
      4. 7.3.4 Serializer Functional Description
        1. 7.3.4.1 Signal Quality Enhancers
          1. 7.3.4.1.1 Serializer VOD Select (VODSEL)
          2. 7.3.4.1.2 Serializer De-Emphasis (DE-EMPH)
        2. 7.3.4.2 EMI Reduction Features
          1. 7.3.4.2.1 Data Randomization and Scrambling
          2. 7.3.4.2.2 Serializer Spread Spectrum Compatibility
        3. 7.3.4.3 Power-Saving Features
          1. 7.3.4.3.1 Serializer Power-Down Feature (PDB)
          2. 7.3.4.3.2 Serializer Stop Clock Feature
          3. 7.3.4.3.3 Serializer 1.8-V or 3.3-V VDDIO Operation
      5. 7.3.5 Deserializer Functional Description
        1. 7.3.5.1 Signal Quality Enhancers
          1. 7.3.5.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 7.3.5.2 EMI Reduction Features
          1. 7.3.5.2.1 Deserializer VOD Select (VODSEL)
          2. 7.3.5.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
          3. 7.3.5.2.3 Deserializer SSCG Generation (Optional)
          4. 7.3.5.2.4 Power-Saving Features
            1. 7.3.5.2.4.1 Deserializer Power-Down Feature (PDB)
            2. 7.3.5.2.4.2 Deserializer Stop Stream SLEEP Feature
            3. 7.3.5.2.4.3 Deserializer 1.8-V or 3.3-V VDDIO Operation
        3. 7.3.5.3 Deserializer Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
        4. 7.3.5.4 Deserializer Oscillator Output (Optional)
      6. 7.3.6 Built-In Self Test (BIST)
        1. 7.3.6.1 Sample BIST Sequence
        2. 7.3.6.2 BER Calculations
      7. 7.3.7 Optional Serial Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
      2. 8.1.2 Live Link Insertion
      3. 8.1.3 Alternate Color or Data Mapping
    2. 8.2 Typical Application
      1. 8.2.1 DS92LV0421 Typical Connection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DS92LV0422 Typical Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 WQFN (LLP) Stencil Guidelines
      2. 10.1.2 Transmission Media
      3. 10.1.3 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NJK|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

NJK Package
36-Pin WQFN
Top View

Pin Functions: DS92LV0421

PIN TYPE(1) DESCRIPTION(2)
NAME NO.
CHANNEL LINK PARALLEL INPUT INTERFACE
RXCLKIN+ 35 I True LVDS Clock Input
This pair must have a 100-Ω termination for standard LVDS levels.
RXCLKIN– 34 I Inverting LVDS Clock Input
This pair must have a 100-Ω termination for standard LVDS levels.
RXIN[3:0]+ 2, 33,
31, 29		 I True LVDS Data Input
This pair must have a 100-Ω termination for standard LVDS levels.
RXIN[3:0]– 1, 32,
30, 28		 I Inverting LVDS Data Input
This pair must have a 100-Ω termination for standard LVDS levels.
CHANNEL LINK II SERIAL OUTPUT INTERFACE
DOUT+ 16 O True Output, CML
The output must be AC-coupled with a 0.1-µF capacitor.
DOUT– 15 O Inverting Output, CML
The output must be AC-coupled with a 0.1-µF capacitor.
CONTROL AND CONFIGURATION
CONFIG[1:0] 10, 9 I Operating Modes: Pin or Register Control, LVCMOS with pulldown.
Determines the device operating mode and interfacing device (see Table 10).
CONFIG[1:0] = 00: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124Q-Q1
CONFIG [1:0] = 11: Interfacing to DS90C124
DE-EMPH 19 I De-emphasis Control: Pin or Register Control, Analog with pullup.
De-emphasis = Open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to Ground or control through register (see Table 2).
MAPSEL 26 I Channel Link Map Select: Pin or Register Control, LVCMOS with pulldown.
MAPSEL = 1, MSB on RXIN3± (see Figure 23).
MAPSEL = 0, LSB on RXIN3± (see Figure 24).
PDB 23 I Power-down Mode input, LVCMOS with pulldown.
PDB = 1, serializer is enabled (normal operation).
See Power Supply Recommendations for more information.
PDB = 0, serializer is powered down
When the serializer is in the power-down state, the driver outputs (DOUT±) are both logic high, the PLL is shut down, and IDD is minimized. Control Registers are RESET.
RES[7:0] 25, 3, 36, 27, 18, 13, 12, 8 I Reserved (tie low), LVCMOS with pulldown.
VODSEL 20 I Differential Driver Output Voltage Select: Pin or Register Control, LVCMOS with pulldown.
VODSEL = 1, CML VOD is ±450 mV, 900 mVp-p (typical): long cable or de-emphasis applications
VODSEL = 0, CML VOD is ±300 mV, 600 mVp-p (typical): short cable (no de-emphasis), low power mode
OPTIONAL BIST MODE
BISTEN 21 I BIST Mode: Optional, LVCMOS with pulldown.
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled (normal operation)
OPTIONAL SERIAL BUS CONTROL
ID[X] 4 I Serial Control Bus Device ID Address Select: Optional, Analog
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 8).
SCL 6 I Serial Control Bus Clock Input: Optional, LVCMOS (open-drain)
SCL requires an external pullup resistor to VDDIO.
SDA 7 I/O Serial Control Bus Data Input or Output: Optional, LVCMOS (open-drain)
SDA requires an external pullup resistor VDDIO.
POWER AND GROUND(3)
DAP GND G DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias.
VDDHS 14 P TX high-speed logic power, 1.8 V ±5%
VDDIO 22 P LVCMOS I/O power and Channel Link I/O power, 1.8 V ±5% or 3.3 V ±10%
VDDL 5 P Logic power, 1.8 V ±5%
VDDP 11 P PLL power, 1.8 V ±5%
VDDRX 24 P RX power, 1.8 V ±5%
VDDTX 17 P Output driver power, 1.8 V ±5%
(1) G = Ground, I = Input, O = Output, and P = Power
(2) 1= HIGH, 0 = LOW
(3) The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage.
RHS Package
48-Pin WQFN
Top View

Pin Functions: DS92LV0422

PIN TYPE(1) DESCRIPTION(2)
NAME NO.
CHANNEL LINK II SERIAL INPUT INTERFACE
CMF 42 I Common-mode filter, Analog
VCM center-tap is a virtual Ground which may be AC-coupled to Ground to increase receiver common mode noise immunity. Recommended value is 4.7 µF or higher.
RIN+ 40 I True Input, CML
The output must be AC-coupled with a 0.1-µF capacitor.
RIN– 41 I Inverting Input, CML
The output must be AC-coupled with a 0.1-µF capacitor.
CHANNEL LINK PARALLEL OUTPUT INTERFACE
TXCLKOUT+ 17 O True LVDS Clock Output
This pair must have a 100-Ω termination for standard LVDS levels.
TXCLKOUT– 18 O Inverting LVDS Clock Output
This pair must have a 100-Ω termination for standard LVDS levels.
TXOUT[3:0]+ 15, 19,
21, 23		 O True LVDS Data Output
This pair must have a 100-Ω termination for standard LVDS levels.
TXOUT[3:0]– 16, 20,
22, 24		 O Inverting LVDS Data Output
This pair must have a 100-Ω termination for standard LVDS levels.
LVCMOS OUTPUTS
LOCK 27 O LOCK Status Output, LVCMOS
LOCK = 1, PLL is locked, output stated determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
See Table 7.
CONTROL AND CONFIGURATION
CONFIG[1:0] 11, 10 I Operating Modes: Pin or Limited Register Control, LVCMOS with pulldown.
Determine the device operating mode and interfacing device. (see Table 10).
CONFIG[1:0] = 00: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421
CONFIG [1:0] = 11: Interfacing to DS90C124
LFMODE 36 I SSCG Low Frequency Mode: Pin or Register Control, LVCMOS with pulldown.
LFMODE = 1, low frequency mode (TXCLKOUT = 10–20 MHz)
LFMODE = 0, high frequency mode (TXCLKOUT = 20–65 MHz)
SSCG not available above 65 MHz.
MAPSEL 34 I Channel Link Map Select: Pin or Register Control, LVCMOS with pulldown.
MAPSEL = 1, MSB on TXOUT3± (see Figure 23).
MAPSEL = 0, LSB on TXOUT3± (see Figure 24).
OEN 30 I Output Enable, LVCMOS with pulldown.
See Table 7 for details.
OSS_SEL 35 I Output Sleep State Select Input, LVCMOS with pulldown.
See Table 7 for details.
PDB 1 I Power-down Mode Input, LVCMOS with pulldown.
PDB = 1, deserializer is enabled (normal operation).
See Power Supply Recommendations for more information.
PDB = 0, deserializer is powered down.
When the deserializer is in the power-down state, the driver outputs (TXOUT±) are in TRI-STATE. Control Registers are RESET.
RES 37 I Reserved (tie low), LVCMOS with pulldown.
SSC[2:0] 7, 3, 2 I Spread Spectrum Clock Generation (SSCG) Range Select, LVCMOS with pulldown.
See Table 5 and Table 6.
VODSEL 33 I Parallel LVDS Driver Output Voltage Select: Pin or Register Control, LVCMOS with pulldown.
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typical)
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typical)
CONTROL AND CONFIGURATION — STRAP PIN
EQ 28 [PASS] I EQ Gain Control of Channel Link II Serial Input, STRAP, LVCMOS with pulldown
EQ = 1, EQ gain is enabled (~13 dB)
EQ = 0, EQ gain is disabled (~1.625 dB)
OPTIONAL BIST MODE
BISTEN 29 I BIST Mode: Optional, LVCMOS with pulldown.
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
PASS 28 O PASS Output (BIST Mode): Optional, LVCMOS
PASS =1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
OPTIONAL SERIAL BUS CONTROL
ID[X] 12 I Serial Control Bus Device ID Address Select: Optional, Analog
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 8).
SCL 5 I Serial Control Bus Clock Input: Optional, LVCMOS (open drain)
SCL requires an external pullup resistor to 3.3 V.
SDA 4 I/O Serial Control Bus Data Input or Output: Optional, LVCMOS (open drain)
SDA requires an external pullup resistor 3.3 V.
POWER AND GROUND(3)
DAP DAP G DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias.
GND 9, 14, 26, 32, 39, 44, 45, 48 G Ground
VDDA 38, 43 P Analog power, 1.8 V ±5%
VDDIO 25 P LVCMOS I/O power and Channel Link I/O power, 1.8 V ± 5% or 3.3 V ±10%
VDDL 6, 31 P Logic power, 1.8 V ±5%
VDDP 8 P PLL power, 1.8 V ±5%
VDDSC 46, 47 P SSCG power, 1.8 V ±5%
VDDTX 13 P Channel Link LVDS parallel output power, 3.3 V ±10%
(1) G = Ground, I = Input, O = Output, and P = Power
(2) 1= HIGH, 0 = LOW
(3) The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage.