SNLS325D May   2010  – December 2016 DS92LV0421 , DS92LV0422

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Serializer DC
    6. 6.6  Electrical Characteristics: Deserializer DC
    7. 6.7  Electrical Characteristics: DC and AC Serial Control Bus
    8. 6.8  Timing Requirements: Serial Control Bus
    9. 6.9  Switching Characteristics: Serializer
    10. 6.10 Switching Characteristics: Deserializer
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Parallel LVDS Data Transfer (Color Bit Mapping Select)
      2. 7.3.2 Serial Data Transfer
      3. 7.3.3 Video Control Signal Filter
      4. 7.3.4 Serializer Functional Description
        1. 7.3.4.1 Signal Quality Enhancers
          1. 7.3.4.1.1 Serializer VOD Select (VODSEL)
          2. 7.3.4.1.2 Serializer De-Emphasis (DE-EMPH)
        2. 7.3.4.2 EMI Reduction Features
          1. 7.3.4.2.1 Data Randomization and Scrambling
          2. 7.3.4.2.2 Serializer Spread Spectrum Compatibility
        3. 7.3.4.3 Power-Saving Features
          1. 7.3.4.3.1 Serializer Power-Down Feature (PDB)
          2. 7.3.4.3.2 Serializer Stop Clock Feature
          3. 7.3.4.3.3 Serializer 1.8-V or 3.3-V VDDIO Operation
      5. 7.3.5 Deserializer Functional Description
        1. 7.3.5.1 Signal Quality Enhancers
          1. 7.3.5.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 7.3.5.2 EMI Reduction Features
          1. 7.3.5.2.1 Deserializer VOD Select (VODSEL)
          2. 7.3.5.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
          3. 7.3.5.2.3 Deserializer SSCG Generation (Optional)
          4. 7.3.5.2.4 Power-Saving Features
            1. 7.3.5.2.4.1 Deserializer Power-Down Feature (PDB)
            2. 7.3.5.2.4.2 Deserializer Stop Stream SLEEP Feature
            3. 7.3.5.2.4.3 Deserializer 1.8-V or 3.3-V VDDIO Operation
        3. 7.3.5.3 Deserializer Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
        4. 7.3.5.4 Deserializer Oscillator Output (Optional)
      6. 7.3.6 Built-In Self Test (BIST)
        1. 7.3.6.1 Sample BIST Sequence
        2. 7.3.6.2 BER Calculations
      7. 7.3.7 Optional Serial Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
      2. 8.1.2 Live Link Insertion
      3. 8.1.3 Alternate Color or Data Mapping
    2. 8.2 Typical Application
      1. 8.2.1 DS92LV0421 Typical Connection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DS92LV0422 Typical Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 WQFN (LLP) Stencil Guidelines
      2. 10.1.2 Transmission Media
      3. 10.1.3 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHS|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from C Revision (April 2013) to D Revision

  • Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table, Thermal Information table, Typical Characteristics section, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Added OpenLDI LVDS as an acceptable parallel interface to the DS92LV024x chipsetGo
  • Changed RXIN and RXCLKIN to TXOUT and TXCLKOUT to correct pin name typos Go
  • Changed output state of deserializer when PDB = 1 to be TRI-STATE, not logic highGo
  • Deleted Power dissipation rows from the Absolute Maximum Ratings tableGo
  • Changed Junction-to-ambient, RθJA, values in Thermal Information table From: 27.4°C/W To: 33.8°C/W (NJK) and From: 27.7°C/W to: 28.8°C/W (RHS)Go
  • Changed Junction-to-case, RθJC(top), values in Thermal Information table From: 4.5°C/W To: 15.8°C/W (NJK) and From: 3.0°C/W To: 9.3°C/W (RHS)Go
  • Deleted note in Electrical Characteristics: Serializer DC table stating that conditions are verified by characterization or design and not tested in production, as this note only applies to a subset of tested parametersGo
  • Changed minimum and maximum value of serializer IIN for LVDS receiver DC specificationGo
  • Changed de-emphasis test condition for serializer IDD supply currentGo
  • Changed IOL condition for serial bus VOL parameter from 3 mA to 0.5 mA Go
  • Changed RPU = 10 kΩ condition for the Serial Control Bus Characteristics of tR and tF Go
  • Changed tPLD footnote to include tDDLT parameterGo
  • Changed notation for serial bit stream UI footnote to clarify 1 UI = 1 / (28 x CLK) Go
  • Changed footnote for deserializer LVDS output units to clarify that parallel interface UI refers to Channel Link format (1 UI = 1 / [7 × CLK]) instead of Channel Link II format (1 UI = 1 / [28 × CLK]) Go
  • Changed DS92LV0422 LVDS Transmitter Pulse Positions image to correct diagram labelingGo
  • Changed parallel interface description of deserializer From: wide parallel output bus To: Channel Link LVDS clock and data busGo
  • Deleted support for output data and clock slew rate control Go
  • Changed CMF cap recommendation from 0.1 µF to 4.7 µFGo
  • Changed SSCG Configuration (LFMODE = L) table and SSCG Configuration (LFMODE = H) table to clarify correct SSC[2:0] behaviorGo
  • Changed PDB, OEN, and OSS_SEL Configuration table to clarify correct behavior with PDB, OEN, and OSS_SEL pinsGo
  • Changed BISTEN detail in BIST Waveforms image so that serializer and deserializer are genericGo
  • Changed description of Serializer VODSEL from Reg 0x00[4] to Reg 0x00[5]Go
  • Changed Serializer Reg 0x00[3:2] description from Reserved to Reverse-Compatibility Mode bitsGo
  • Changed Deserializer Reg 0x00[3:2] description from Reserved to Reverse-Compatibility Mode bitsGo

Changes from B Revision (April 2013) to C Revision

  • Changed layout of National Semiconductor Data Sheet to TI formatGo