7.3.1 Serializer Functional Description

The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins or through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that provides randomization, scrambling, and DC Balancing of the data. The Ser includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.

7.3.1.2 Integrated Signal Conditioning Features — Ser

7.3.1.2.1 Ser — VOD Select (VODSEL)

The Ser differential output voltage may be increased by setting the VODSEL Pin High. When VODSEL is Low, the VOD is at the standard (default) level. When VODSEL is High, the VOD is increased in level. The increased VOD is useful in extremely high noise environments and also on extra long cable length applications. When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially with the larger de-emphasis settings. This feature may be controlled by the external Pin or by register.

Table 1. Differential Output Voltage

INPUT	EFFECT
VODSEL	VOD mV	VOD mVp-p
H	±420	840
L	±280	560

7.3.1.2.2 Ser — De-Emphasis (De-Emph)

The De-Emph Pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the Ser drives. This is useful to counteract loading effects of long or lossy cables. This Pin should be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this Pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using De-Emphasis it is recommended to set VODSEL = H.

Table 2. De-Emphasis Resistor Value

RESISTOR VALUE (kΩ)	DE-EMPHASIS SETTING
Open	Disabled
0.6	- 12 dB
1.0	- 9 dB
2.0	- 6 dB
5.0	- 3 dB

Figure 21. De-Emph vs. R Value

7.3.2 Deserializer Functional Description

The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins and strap Pins or through the optional serial control bus. The Des features enhance signal quality on the link with an integrated equalizer on the serial input and Channel Link II data encoding which provides randomization, scrambling, and DC balancing of the data. The Des includes multiple features to reduce EMI associated with data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock generation (SSCG) support and output clock and data slew rate select. The Des features power saving features with a power down mode, and optional LVCMOS (1.8 V) interface compatibility.

7.3.2.2 EMI Reduction Features

7.3.2.2.1 Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA)

The parallel data outputs and clock outputs of the deserializer feature selectable output slew rates. The slew rate of the CLKOUT Pin is controlled by the strap Pin or register OS_CLKOUT, while the data outputs (DO[23:0] and CO[3:1]) are controlled by the strap Pin or register OS_DATA. When OS_CLKOUT/DATA = HIGH, the maximum slew rate is selected. When the OS_CLKOUT/DATA = LOW, the minimum slew rate is selected. Use the higher slew rate when driving longer traces or a heavier capacitive load.

7.3.2.2.2 Des — Common Mode Filter Pin (CMF) — Optional

The Des provides access to the center tap of the internal termination. A capacitor may be placed on this Pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 4.7 µF capacitor may be connected to this Pin to Ground.

7.3.2.2.3 Des — SSCG Generation — Optional

The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up to 100 kHz modulations is available. See Table 4. This feature may be controlled by external STRAP Pins or by register.

Table 4. SSCG Configuration (LF_MODE = L) — Des Output

SSC[3:0] INPUTS LF_MODE = L (20 - 50 MHz)				RESULT
SSC3	SSC2	SSC1	SSC0	fdev (%)	fmod (kHz)
L	L	L	L	NA	Disable
L	L	L	H	±0.5	CLK/2168
L	L	H	L	±1.0
L	L	H	H	±1.5
L	H	L	L	±2.0
L	H	L	H	±0.5	CLK/1300
L	H	H	L	±1.0
L	H	H	H	±1.5
H	L	L	L	±2.0
H	L	L	H	±0.5	CLK/868
H	L	H	L	±1.0
H	L	H	H	±1.5
H	H	L	L	±2.0
H	H	L	H	±0.5	CLK/650
H	H	H	L	±1.0
H	H	H	H	±1.5

Table 5. SSCG Configuration (Lf_mode = H) — Des Output

SSC[3:0] INPUTS LH_MODE = H (5 - 20 MHz)				RESULT
SSC3	SSC2	SSC1	SSC0	fdev (%)	fmod (kHz)
L	L	L	L	NA	Disable
L	L	L	H	±0.5	CLK/620
L	L	H	L	±1.0
L	L	H	H	±1.5
L	H	L	L	±2.0
L	H	L	H	±0.5	CLK/370
L	H	H	L	±1.0
L	H	H	H	±1.5
H	L	L	L	±2.0
H	L	L	H	±0.5	CLK/258
H	L	H	L	±1.0
H	L	H	H	±1.5
H	H	L	L	±2.0
H	H	L	H	±0.5	CLK/192
H	H	H	L	±1.0
H	H	H	H	±1.5

Figure 22. SSCG Waveform

7.3.2.2.4 1.8 V or 3.3 V VDDIO Operation

The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (V_DDIO) for target host compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.

7.3.2.5 Des — Oscillator Output — Optional

The Des provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the external Pin or by register. See Table 7 and Table 8.

Table 6. OSS_SEL And PDB Configuration — Des Outputs

INPUTS			OUTPUTS
SERIAL INPUT	PDB	OSS_SEL	CLKOUT	DO[23:0], CO1, CO2, CO3	LOCK	PASS
X	L	L	Z	Z	Z	Z
X	L	H	Z	Z	Z	Z
Static	H	L	L	L	L	L
Static	H	H	Z	Z*	L	L
Active	H	X	Active	Active	H	H
*NOTE — If Pin is strapped HIGH the output will be pulled up

Table 7. OSC (Oscillator) Mode — Des Output

INPUTS	OUTPUTS
EMBEDDED CLK	CLKOUT	DO[23:0]/CO1/CO2/CO3	LOCK	PASS
NOTE *	OSC Output	L	L	H
Present	Toggling	Active	H	H
* NOTE — Absent and OSC_SEL ≠ 000

Figure 23. Des Outputs With Output State Select Low (OSS_SEL = L)

Figure 24. Des Outputs With Output State Select High (OSS_SEL = H)

Table 8. OSC_SEL (Oscillator) Configuration

OSC_SEL[2:0] INPUTS			CLKOUT OSCILLATOR FREQUENCY
OSC_SEL2	OSC_SEL1	OSC_SEL0
L	L	L	Off – Feature Disabled – Default
L	L	H	50 MHz ±40%
L	H	L	25 MHz ±40%
L	H	H	16.7 MHz ±40%
H	L	L	12.5 MHz ±40%
H	L	H	10 MHz ±40%
H	H	L	8.3 MHz ±40%
H	H	H	6.3 MHz ±40%

Figure 25. Des Outputs With Output State High And Clk Output Oscillator Option Enabled

7.3.2.6 Des — OP_LOW — Optional

The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output, at a LOW state. When the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while LOCK = LOW. The user must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the release of the outputs can only occur when LOCK is HIGH. The OP_LOW strap option is assigned to the PASS Pin, at Pin location 42.

Restrictions on other straps:

1. Other strap options should not be used in order to keep the data and clock outputs at a true logic LOW state. Other features should be selected through the I2C register interface.
2. The OSS_SEL feature is not available when OP_LOW is enabled.

Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE before PDB toggles HIGH because the OP-LOW strap value has not been recognized until the DS92LV2412 powers up. Figure 26 shows the user controlled release of the OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 27 shows the user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of OP_LOW can only occur when LOCK is HIGH.

Figure 26. OP_LOW Auto Set

Figure 27. OP_LOW Manual Set/Reset

7.3.3 Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST mode only a input clock is required along with control to the Ser and Des BISTEN input Pins. The Ser outputs a test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors. A PASS output Pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the Des BISTEN Pin. During the BIST duration, the deserializer data outputs toggle with a checkerboard pattern.

Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1/2/3).

Note: In order to use BIST mode, the BISTEN Pin must be pulled high and REG = 0. The serializer cannot be placed in BIST mode if REG = 1, as this will cause the DS92LV2411 to ignore the pin input voltage.

7.3.3.1 Sample BIST Sequence

See Figure 28 for the BIST mode flow diagram.

Step 1: Place the DS92LV2411 Ser in BIST Mode by setting Ser BISTEN = H. For the DS92LV2411 Ser or DS99R421 Channel Link II Ser BIST Mode is enabled via the BISTEN Pin. A CLKIN is required for BIST. When the Des detects the BIST mode pattern and command (DCA and DCB code) the data and control signal outputs are shut off.

Step 2: Place the DS92LV2412 Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS Pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the Des BISTEN Pin is set Low. The Des stops checking the data and the final test result is held on the PASS Pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.

Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal operation.

Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).

Figure 28. BIST Mode Flow Diagram

7.3.3.2 BER Calculations

It is possible to calculate the approximate Bit Error Rate (BER). The following is required:

• Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)

The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we assume a 50 MHz clock, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.39 X 10E-12

The BIST mode runs a check on the data payload bits. The LOCK Pin also provides a link status. It the recovery of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK Pin will switch Low. The combination of the LOCK and At-Speed BIST PASS Pin provides a powerful tool for system evaluation and performance monitoring.

Figure 29. BIST Waveforms

7.4.1 Data Transfer

The DS92LV2411 / DS92LV2412 chipset will transmit and receive a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The remaining 26 bit spaces contain the scrambled, encoded and DC-Balanced serial data.

7.4.2 Serializer and Deserializer Operating Modes and Reverse Compatibility (Config[1:0])

The DS92LV2411 / DS92LV2412 chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] Pins on the Ser or Des as shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or disabled in the Normal mode. These configuration modes are selectable the control Pins only.

7.4.3 Video Control Signal Filter — Serializer and Deserializer

When operating the devices in Normal Mode, the Control Signals have the following restrictions:

• Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 parallel clocks or longer.
• Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock cycles.

Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause a visual error in display applications. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See Figure.

7.5.1 Optional Serial Bus Control

The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap Pins. A write of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap Pins. Multiple devices may share the serial control bus since multiple addresses are supported. See Figure 30.

The serial bus is comprised of three Pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull up resistor to V_DDIO. For most applications a 4.7 k pull up resistor to V_DDIO may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

Figure 30. Serial Control Bus Connection

The third Pin is the ID[X] Pin. This Pin sets one of four possible device addresses. As shown in Figure 30 , Table 11 and Table 12 different Resistor values could be used to set different SMBUS addresses.

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure 31

Figure 31. Start and Stop Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 32 and a WRITE is shown in Figure 33.

If the Serial Bus is not required, the three Pins may be left open (NC).

Figure 32. Serial Control Bus — Read

Figure 33. Serial Control Bus — Write

Table 13. Serializer — Serial Bus Control Registers

Table 14. Deserializer — Serial Bus Control Registers