SNLS321C May   2010  – May 2016 DS92LV2421 , DS92LV2422

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Serializer DC
    6. 6.6  Electrical Characteristics - Deserializer DC
    7. 6.7  Electrical Characteristics - DC and AC Serial Control Bus
    8. 6.8  Timing Requirements - DC and AC Serial Control Bus
    9. 6.9  Timing Requirements - Serializer for CLKIN
    10. 6.10 Timing Requirements - Serial Control Bus
    11. 6.11 Switching Characteristics - Serializer
    12. 6.12 Switching Characteristics - Deserializer
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Data Transfer
      2. 7.3.2 Video Control Signal Filter - Serializer and Deserializer
      3. 7.3.3 Serializer Functional Description
        1. 7.3.3.1 EMI Reduction Features
          1. 7.3.3.1.1 Data Randomization and Scrambling
          2. 7.3.3.1.2 Serializer Spread Spectrum Compatibility
        2. 7.3.3.2 Signal Quality Enhancers
          1. 7.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 7.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 7.3.3.3 Power-Saving Features
          1. 7.3.3.3.1 Serializer Power-Down Feature (PDB)
          2. 7.3.3.3.2 Serializer Stop Clock Feature
          3. 7.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
          4. 7.3.3.3.4 Deserializer Power-Down Feature (PDB)
          5. 7.3.3.3.5 Deserializer Stop Stream SLEEP Feature
        4. 7.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 7.3.3.5 Optional Serial Bus Control
        6. 7.3.3.6 Optional BIST Mode
      4. 7.3.4 Deserializer Functional Description
        1. 7.3.4.1  Signal Quality Enhancers
          1. 7.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 7.3.4.2  EMI Reduction Features
          1. 7.3.4.2.1 Deserializer Output Slew Rate Select (OS_CLKOUT/OS_DATA)
          2. 7.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
          3. 7.3.4.2.3 Deserializer SSCG Generation (Optional)
          4. 7.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 7.3.4.3  Deserializer Clock-Data Recovery Status Flag (LOCK) And Output State Select (OSS_SEL)
        4. 7.3.4.4  Deserializer Oscillator Output (Optional)
        5. 7.3.4.5  Deserializer OP_LOW (Optional)
        6. 7.3.4.6  Deserializer Clock Edge Select (RFB)
        7. 7.3.4.7  Deserializer Control Signal Filter (Optional)
        8. 7.3.4.8  Deserializer Low Frequency Optimization (LF_Mode)
        9. 7.3.4.9  Deserializer Map Select
        10. 7.3.4.10 Deserializer Strap Input Pins
        11. 7.3.4.11 Optional Serial Bus Control
        12. 7.3.4.12 Optional BIST Mode
      5. 7.3.5 Built-In Self Test (BIST)
        1. 7.3.5.1 Sample BIST Sequence
        2. 7.3.5.2 BER Calculations
      6. 7.3.6 Optional Serial Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
      2. 8.1.2 Live Link Insertion
      3. 8.1.3 Alternate Color / Data Mapping
    2. 8.2 Typical Applications
      1. 8.2.1 DS92LV2421 Typical Connection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 DS92LV2422 Typical Connection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 WQFN (LLP) Stencil Guidelines
      2. 10.1.2 Transmission Media
      3. 10.1.3 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RHS Package
48-Pin WQFN
Top View

Pin Functions: DS92LV2421 (Serializer)

PIN TYPE(1) DESCRIPTION(2)
NAME NO.
LVCMOS PARALLEL INTERFACE
DI[7:0] 34, 33, 32, 29, 28, 27, 26, 25 I Parallel interface data input pins, LVCMOS with pulldown.
For 8-bit RED display: DI7 = R7 – MSB, DI0 = R0 – LSB.
DI[15:8] 42, 41, 40, 39, 38, 37, 36, 35 I Parallel interface data input pins, LVCMOS with pulldown.
For 8-bit GREEN display: DI15 = G7 – MSB, DI8 = G0 – LSB.
DI[23:16] 2, 1, 48, 47, 46, 45, 44, 43 I Parallel interface data input pins, LVCMOS with pulldown.
For 8-bit BLUE display: DI23 = B7 – MSB, DI16 = B0 – LSB.
CI1 5 I Control signal input, LVCMOS with pulldown.
For display or video application: CI1 = Data enable input.
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting.
CI2 3 I Control signal input, LVCMOS with pulldown.
For display or video application: CI2 = Horizontal sync input.
Control signal pulse width must be 3 clocks or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting.
CI3 4 I Control signal input, LVCMOS with pulldown.
For display or video application: CI3 = Vertical sync input.
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is 130 clock cycles wide.
CLKIN 10 I Clock input, LVCMOS with pulldown.
Latch or data strobe edge set by RFB pin.
CONTROL AND CONFIGURATION
PDB 21 I Power-down mode input, LVCMOS with pulldown.
PDB = 1, serializer is enabled (normal operation).
Refer to Power-Up Requirements and PDB Pin.
PDB = 0, serializer is powered down. When the serializer is in the power-down state, the driver outputs (DOUT±) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL 24 I Differential driver output voltage select (this can also be control by I2C register access), LVCMOS with pulldown.
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typical) — long cable or de-emphasis apps.
VODSEL = 0, LVDS VOD is ±280 mV, 560 mVp-p (typical) — short cable (no de-emphasis), low power mode.
De-Emph 23 I De-emphasis control (this can also be controlled by I2C register access), analog with pullup.
De-emphasis = open (float) - disabled.
To enable de-emphasis, tie a resistor from this pin to GND or control through register (see Table 3).
RFB 11 I Clock input latch or data strobe edge select (this can also be controlled by I2C register access), LVCMOS with pulldown.
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
CONFIG[1:0] 13, 12 I LVCMOS with pulldown.
00: Control Signal Filter DISABLED.
01: Control Signal Filter ENABLED.
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q-Q1.
11: Reverse compatibility mode to interface with the DS90C124.
ID[X] 6 I I2C serial control bus device ID address select (optional), analog.
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 11).
SCL 8 I I2C serial control bus clock input (optional), LVCMOS.
SCL requires an external pullup resistor to VDDIO.
SDA 9 I/O I2C serial control bus data input or output (optional), LVCMOS (open drain).
SDA requires an external pullup resistor VDDIO.
BISTEN 31 I BIST mode (optional), LVCMOS with pulldown.
BISTEN = 0, BIST is disabled (normal operation).
BISTEN = 1, BIST is enabled.
RES[2:0] 18, 16, 15 I Reserved (tie low), LVCMOS with pulldown.
CHANNEL-LINK II – CML SERIAL INTERFACE
DOUT+ 20 O Noninverting output, CML.
The output must be AC-coupled with a 0.1-µF capacitor.
DOUT– 19 O Inverting output, CML.
The output must be AC-coupled with a 0.1-µF capacitor.
POWER AND GROUND(3)
VDDL 7 P Logic power, 1.8 V ± 5%
VDDP 14 P PLL power, 1.8 V ± 5%
VDDHS 17 P TX high-speed logic power, 1.8 V ± 5%
VDDTX 22 P Output driver power, 1.8 V ± 5%
VDDIO 30 P LVCMOS I/O power, 1.8 V ± 5% or 3.3 V ± 10%
GND DAP G DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias.
(1) G = Ground, I = Input, O = Output, and P = Power
(2) 1= HIGH, 0 = LOW
(3) The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
NKB Package
60-Pin WQFN
Top View

Table 1. Pin Functions: DS92LV2422 (Deserializer)

PIN TYPE(1) DESCRIPTION(2)
NAME NO.
LVCMOS PARALLEL INTERFACE
DO[7:0] 33, 34, 35, 36, 37, 39, 40, 41 I/O Parallel interface data output pins, STRAP and LVCMOS.
For 8-bit RED display: DO7 = R7 – MSB, DO0 = R0 – LSB.
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins are inputs during power-up (see Deserializer Strap Input Pins).
DO[15:8] 20, 21, 22, 23, 25, 26, 27, 28 I/O Parallel interface data output pins, STRAP and LVCMOS.
For 8-bit GREEN display: DO15 = G7 – MSB, DO8 = G0 – LSB.
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins are inputs during power-up (see Deserializer Strap Input Pins).
DO[23:16] 9, 10, 11, 12, 14, 17, 18, 19 I/O Parallel interface data input pins, STRAP and LVCMOS.
For 8-bit BLUE display: DO23 = B7 – MSB, DO16 = B0 – LSB.
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins are inputs during power-up (see Deserializer Strap Input Pins).
CO1 6 O Control signal output, LVCMOS.
For display or video application: CO1 = Data enable output.
Control signal pulse width must be 3 clocks or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting.
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7).
CO2 8 O Control signal output, LVCMOS.
For display or video application: CO2 = Horizontal sync output.
Control signal pulse width must be 3 clocks or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter setting.
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7).
CO3 7 O Control signal output, LVCMOS.
For display or video application: CO3 = Vertical sync output.
CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is 130 clock cycles wide.
The CONFIG[1:0] pins have no effect on the CO3 signal.
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7).
CLKOUT 5 O Pixel clock output, LVCMOS.
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7). Data strobe edge set by RFB.
LOCK 32 O LOCK status output, LVCMOS.
LOCK = 1, PLL is locked, outputs are active
LOCK = 0, PLL is unlocked, DO[23:0], CO1, CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (see Table 7).
May be used as link status or to flag when video data is active (ON/OFF).
PASS 42 O PASS output (BIST mode), LVCMOS.
PASS = 1, error free transmission.
PASS = 0, one or more errors were detected in the received payload.
Route to test point for monitoring, or leave open if unused.
CONTROL AND CONFIGURATION – STRAP PINS(3)
CONFIG[1:0] 10 [DO22],
9 [DO23]		 I STRAP or LVCMOS with pulldown.
00: Control Signal Filter DISABLED.
01: Control Signal Filter ENABLED.
10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241-Q1.
11: Reverse compatibility mode to interface with the DS90C241.
LF_MODE 12 [DO20] I SSCG low frequency mode, STRAP or LVCMOS with pulldown.
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
LF_MODE = 1, SSCG in low frequency mode (CLK = 10 to 20 MHz).
LF_MODE = 0, SSCG in high frequency mode (CLK = 20 to 65 MHz).
This can also be controlled by I2C register access.
OS_CLKOUT 11 [DO21] I Output CLKOUT slew select, STRAP or LVCMOS with pulldown.
OS_CLKOUT = 1, increased CLKOUT slew rate.
OS_CLKOUT = 0, normal CLKOUT slew rate (default).
This can also be controlled by I2C register access.
OS_DATA 14 [DO19] I Output DO[23:0], CO1, CO2, CO3 slew select; STRAP or LVCMOS with pulldown.
OS_DATA = 1, Increased DO slew rate.
OS_DATA = 0, Normal DO slew rate (default).
This can also be controlled by I2C register access.
OP_LOW 42 [PASS] I Outputs held low when LOCK = 1, STRAP or LVCMOS with pulldown.
NOTE: Do not use any other strap options with this strap function enabled.
OP_LOW = 1, all outputs are held low during power up until released by programming OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE (see Figure 30 and Figure 31).
OP_LOW = 0, all outputs toggle normally as soon as LOCK goes high (default).
This can also be controlled by I2C register access.
OSS_SEL 17 [DO18] I Output sleep state select, STRAP or LVCMOS with pulldown.
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in power down (see Table 7).
NOTE: OSS_SEL strap cannot be used if OP_LOW = 1.
This can also be controlled by I2C register access.
RFB 18 [DO17] I Clock output strobe edge select, STRAP or LVCMOS with pulldown.
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
EQ[3:0] 20 [DO15],
21 [DO14],
22 [DO13],
23 [DO12]		 I Receiver input equalization, STRAP or LVCMOS with pulldown (see Table 4).
This can also be controlled by I2C register access.
OSC_SEL[2:0] 26 [DO10],
27 [DO9],
28 [DO8]		 I Oscillator select, STRAP or LVCMOS with pulldown (see Table 8 and Table 9).
This can also be controlled by I2C register access.
SSC[3:0] 34 [DO6],
35 [DO5],
36 [DO4],
37 [DO3]		 I Spread spectrum clock generation (SSCG) range select, STRAP or LVCMOS with pulldown (see Table 5 and Table 6).
This can also be controlled by I2C register access.
MAP_SEL[1:0] 40 [D],
41 [D]		 I Bit mapping reverse compatibility or DS90UR241 options, STRAP or LVCMOS with pulldown.
Pin or register control. Default setting is 00'b (see Table 10).
CONTROL AND CONFIGURATION
PDB 59 I Power-down mode input, LVCMOS with pulldown.
PDB = 1, deserializer is enabled (normal operation). Refer to Power-Up Requirements and PDB Pin.
PDB = 0, deserializer is in power down.
When the deserializer is in the power-down state, the LVCMOS output state is determined by Table 7. Control registers are RESET.
ID[X] 56 I I2C serial control bus device ID Address Select (optional), analog.
Resistor to ground and 10-kΩ pullup to 1.8-V rail (see Table 11).
SCL 3 I I2C serial control bus clock input (optional), LVCMOS.
SCL requires an external pullup resistor to VDDIO.
SDA 2 I/O I2C serial control bus data input or output (optional), LVCMOS open drain.
SDA requires an external pullup resistor to VDDIO.
BISTEN 44 I BIST enable input (optional), LVCMOS with pulldown.
BISTEN = 0, BIST is disabled (normal operation).
BISTEN = 1, BIST is enabled.
RES 47 I Reserved (tie low), LVCMOS with pulldown.
NC 1, 15, 16, 30, 31, 45, 46, 60 — Not connected, leave pin open (float).
CHANNEL-LINK II — CML SERIAL INTERFACE
RIN+ 49 I True input, CML. The input must be AC-coupled with a 0.1-μF capacitor.
RIN- 50 I Inverting input, CML. The input must be AC-coupled with a 0.1-μF capacitor.
CMF 51 I Common-mode filter, analog.
VCM center-tap is a virtual ground which may be AC-coupled to ground to increase receiver common mode noise immunity. Recommended value is 4.7 μF or higher.
ROUT+ 52 O True output (receive signal after the equalizer), CML.
NC if not used or connect to test point for monitor. Requires I2C control to enable.
ROUT- 53 O Inverting output (receive signal after the equalizer), CML.
NC if not used or connect to test point for monitor. Requires I2C control to enable.
POWER AND GROUND(4)
VDDL 29 P Logic power, 1.8 V ± 5%
VDDIR 48 P Input power, 1.8 V ± 5%
VDDR 43, 55 P RX high-speed logic power, 1.8 V ± 5%
VDDSC 4, 58 P SSCG power, 1.8 V ± 5%
VDDPR 57 P PLL power, 1.8 V ± 5%
VDDCMLO 54 P RX high-speed logic power, 1.8 V ± 5%
VDDIO 13, 24, 38 P LVCMOS I/O power, 1.8 V ± 5% or 3.3 V ± 10% (VDDIO)
GND DAP G DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
(1) G = Ground, I = Input, O = Output, and P = Power
(2) 1= HIGH, 0 = LOW
(3) For a high state, use a 10-kΩ pullup to VDDIO; for a low state, the IO includes an internal pull down. The strap pins are read upon power-up and set device configuration. Pin number DO[23:0] listed along with shared data output name in square brackets.
(4) The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.