SNLS321C May   2010  – May 2016 DS92LV2421 , DS92LV2422

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Serializer DC
    6. 6.6  Electrical Characteristics - Deserializer DC
    7. 6.7  Electrical Characteristics - DC and AC Serial Control Bus
    8. 6.8  Timing Requirements - DC and AC Serial Control Bus
    9. 6.9  Timing Requirements - Serializer for CLKIN
    10. 6.10 Timing Requirements - Serial Control Bus
    11. 6.11 Switching Characteristics - Serializer
    12. 6.12 Switching Characteristics - Deserializer
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Data Transfer
      2. 7.3.2 Video Control Signal Filter - Serializer and Deserializer
      3. 7.3.3 Serializer Functional Description
        1. 7.3.3.1 EMI Reduction Features
          1. 7.3.3.1.1 Data Randomization and Scrambling
          2. 7.3.3.1.2 Serializer Spread Spectrum Compatibility
        2. 7.3.3.2 Signal Quality Enhancers
          1. 7.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 7.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 7.3.3.3 Power-Saving Features
          1. 7.3.3.3.1 Serializer Power-Down Feature (PDB)
          2. 7.3.3.3.2 Serializer Stop Clock Feature
          3. 7.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
          4. 7.3.3.3.4 Deserializer Power-Down Feature (PDB)
          5. 7.3.3.3.5 Deserializer Stop Stream SLEEP Feature
        4. 7.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 7.3.3.5 Optional Serial Bus Control
        6. 7.3.3.6 Optional BIST Mode
      4. 7.3.4 Deserializer Functional Description
        1. 7.3.4.1  Signal Quality Enhancers
          1. 7.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 7.3.4.2  EMI Reduction Features
          1. 7.3.4.2.1 Deserializer Output Slew Rate Select (OS_CLKOUT/OS_DATA)
          2. 7.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
          3. 7.3.4.2.3 Deserializer SSCG Generation (Optional)
          4. 7.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 7.3.4.3  Deserializer Clock-Data Recovery Status Flag (LOCK) And Output State Select (OSS_SEL)
        4. 7.3.4.4  Deserializer Oscillator Output (Optional)
        5. 7.3.4.5  Deserializer OP_LOW (Optional)
        6. 7.3.4.6  Deserializer Clock Edge Select (RFB)
        7. 7.3.4.7  Deserializer Control Signal Filter (Optional)
        8. 7.3.4.8  Deserializer Low Frequency Optimization (LF_Mode)
        9. 7.3.4.9  Deserializer Map Select
        10. 7.3.4.10 Deserializer Strap Input Pins
        11. 7.3.4.11 Optional Serial Bus Control
        12. 7.3.4.12 Optional BIST Mode
      5. 7.3.5 Built-In Self Test (BIST)
        1. 7.3.5.1 Sample BIST Sequence
        2. 7.3.5.2 BER Calculations
      6. 7.3.6 Optional Serial Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
      2. 8.1.2 Live Link Insertion
      3. 8.1.3 Alternate Color / Data Mapping
    2. 8.2 Typical Applications
      1. 8.2.1 DS92LV2421 Typical Connection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 DS92LV2422 Typical Connection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 WQFN (LLP) Stencil Guidelines
      2. 10.1.2 Transmission Media
      3. 10.1.3 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

9.1 Power-Up Requirements and PDB Pin

The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a 22-µF capacitor to GND to delay the PDB input signal.