SNLS321C May 2010 – May 2016 DS92LV2421 , DS92LV2422
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VDDn (1.8 V) | –0.3 | 2.5 | V | |
Supply voltage, VDDIO | –0.3 | 4 | V | |
LVCMOS I/O voltage | –0.3 | VDDIO + 0.3 | V | |
Receiver input voltage | –0.3 | VDD + 0.3 | V | |
Driver output voltage | –0.3 | VDD + 0.3 | V | |
48L RHS package | Maximum power dissipation capacity at 25°C | 225 | mW | |
Derate above 25°C | 1 / RθJA | mW/°C | ||
60L NKB package | Maximum power dissipation capacity at 25°C | 525 | mW | |
Derate above 25°C | 1 / RθJA | mW/°C | ||
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±8000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | ||||
Machine model (MM) | ±250 | ||||
IEC 61000-4-2 contact discharge | DOUT+, DOUT- | ≥±8000 | |||
RIN+, RIN- | ≥±8000 | ||||
IEC 61000-4-2 air-gap discharge | DOUT+, DOUT- | ≥±25000 | |||
RIN+, RIN- | ≥±25000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDDn | Supply voltage | 1.71 | 1.8 | 1.89 | V |
VDDIO | LVCMOS supply voltage | 1.71 | 1.8 | 1.89 | V |
VDDIO | LVCMOS supply voltage | 3 | 3.3 | 3.6 | V |
Clock frequency | 10 | 75 | MHz | ||
Supply noise(1) | 50 | mVp-p | |||
TA | Operating free-air temperature | –40 | 25 | 85 | °C |
THERMAL METRIC(1) | DS92LV2421 | DS92LV2422 | UNIT | |
---|---|---|---|---|
RHS (WQFN) | NKB (WQFN) | |||
48 PINS | 60 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 30.3 | 26.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance(2) | 11.5 | 9.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 7.3 | 6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 7.3 | 6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.7 | 1.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
LVCMOS INPUT DC SPECIFICATIONS | ||||||||
VIH | High level input voltage | VDDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | 2.2 | VDDIO | V | |||
VDDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | 0.65 × VDDIO | VDDIO | ||||||
VIL | Low level input voltage | VDDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | GND | 0.8 | V | |||
VDDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | GND | 0.35 × VDDIO | ||||||
IIN | Input current | VIN = 0 V or VDDIO (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins) | VDDIO = 3 V to 3.6 V | –15 | ±1 | 15 | μA | |
VDDIO = 1.7 V to 1.89 V | –15 | ±1 | 15 | |||||
CML DRIVER DC SPECIFICATIONS | ||||||||
VOD | Differential output voltage | RL = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins) | VODSEL = 0 | ±205 | ±280 | ±355 | mV | |
VODSEL = 1 | ±320 | ±420 | ±520 | |||||
VODp-p | Differential output voltage (DOUT+) – (DOUT-) |
RL = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins) | VODSEL = 0 | 560 | mVp-p | |||
VODSEL = 1 | 840 | |||||||
ΔVOD | Output voltage unbalance | RL = 100 Ω, de-emphasis = disabled, VODSEL = L (DOUT+ and DOUT– pins) | 1 | 50 | mV | |||
VOS | Offset voltage (single-ended) |
At TP A and B (see Figure 1), RL = 100 Ω, de-emphasis = disabled (DOUT+ and DOUT– pins) | VODSEL = 0 | 1.65 | V | |||
VODSEL = 1 | 1.575 | |||||||
ΔVOS | Offset voltage unbalance (single-ended) |
At TP A and B (see Figure 1), RL = 100 Ω, de-emphasis = disabled (DOUT+ and DOUT– pins) |
1 | mV | ||||
IOS | Output short circuit current | DOUT± = 0 V, de-emphasis = disabled, VODSEL = 0 (DOUT+ and DOUT– pins) |
–36 | mA | ||||
RTO | Internal output termination resistor | DOUT+ and DOUT– pins | 80 | 100 | 120 | Ω | ||
SUPPLY CURRENT | ||||||||
IDDT1 | Serializer supply current (includes load current) |
RL = 100 Ω, CLKIN = 75 MHz, checker board pattern, de-emphasis = 3 kΩ, VODSEL = H (see Figure 9) |
VDD = 1.89 V | 75 | 90 | mA | ||
VDDIO = 1.89 V | 3 | 5 | ||||||
IDDIOT1 | VDDIO = 3.6 V | 11 | 15 | |||||
IDDT2 | Serializer supply current (includes load current) |
RL = 100 Ω, CLKIN = 75 MHz, checker board pattern, de-emphasis = 6 kΩ, VODSEL = L (see Figure 9) |
VDD = 1.89 V | 65 | 80 | mA | ||
VDDIO = 1.89 V | 3 | 5 | ||||||
IDDIOT2 | VDDIO = 3.6 V | 11 | 15 | |||||
IDDZ | Serializer supply current power-down | PDB = 0 V, All other LVCMOS Inputs = 0 V | VDD = 1.89 V | 40 | 1000 | µA | ||
VDDIO = 1.89 V | 5 | 10 | ||||||
IDDIOZ | VDDIO = 3.6 V | 10 | 20 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
3.3-V I/O LVCMOS DC SPECIFICATIONS (VDDIO = 3 V TO 3.6 V) | |||||||
VIH | High level input voltage | PDB and BISTEN pins | 2.2 | VDDIO | V | ||
VIL | Low level input voltage | PDB and BISTEN pins | GND | 0.8 | V | ||
IIN | Input current | VIN = 0 V or VDDIO (PDB and BISTEN pins) | −15 | ±1 | 15 | μA | |
VOH | High level output voltage | IOH = −2 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | 2.4 | VDDIO | V | ||
VOL | Low level output voltage | IOL = 3 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | GND | 0.4 | V | ||
IOS | Output short circuit current | VDDIO = 3.3 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin) | 36 | mA | |||
Output short circuit current | VDDIO = 3.3 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (output pins) | 37 | |||||
IOZ | TRI-STATE output current | PDB = 0 V, OSS_SEL = 0 V, VOUT = H (output pins) | −15 | 15 | µA | ||
1.8-V I/O LVCMOS DC SPECIFICATIONS (VDDIO = 1.71 V to 1.89 V) | |||||||
VIH | High level input voltage | PDB and BISTEN pins | 1.235 | VDDIO | V | ||
VIL | Low level input voltage | PDB and BISTEN pins | GND | 0.595 | V | ||
IIN | Input current | VIN = 0 V or VDDIO (PDB and BISTEN pins) | −15 | ±1 | 15 | μA | |
VOH | High level output voltage | IOH = –2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | VDDIO – 0.45 | VDDIO | V | ||
VOL | Low level output voltage | IOL = 2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins) | GND | 0.45 | V | ||
IOS | Output short circuit current | VDDIO = 1.8 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin) | 18 | mA | |||
Output short circuit current | VDDIO = 1.8 V, VOUT = 0 V, OS_CLKOUT/DATA = L/H (output pins) | 18 | |||||
IOZ | TRI-STATE output current | PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO (output pins) | –15 | 15 | µA | ||
CML RECEIVER DC SPECIFICATIONS | |||||||
VTH | Differential input threshold high voltage | VCM = 1.2 V, RIN+ and RIN- pins (Internal VBIAS) | 50 | mV | |||
VTL | Differential input threshold low voltage | VCM = 1.2 V, RIN+ and RIN- pins (Internal VBIAS) | –50 | mV | |||
VCM | Common mode voltage | RIN+ and RIN- pins (Internal VBIAS) | 1.2 | V | |||
IIN | Input current | VIN = 0 V or VDDIO, RIN+ and RIN- pins | –15 | 15 | µA | ||
RTI | Internal input termination resistor | RIN+ and RIN- pins | 80 | 100 | 120 | Ω | |
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS (EQ TEST PORT(1)) | |||||||
VOD | Differential output voltage | ROUT+ and ROUT- pins, RL = 100 Ω | 542 | mV | |||
VOS | Offset voltage (single-ended) |
ROUT+ and ROUT- pins, RL = 100 Ω | 1.4 | V | |||
RT | Internal termination resistor | ROUT+ and ROUT- pins | 80 | 100 | 120 | Ω | |
SUPPLY CURRENT | |||||||
IDD1 | Deserializer supply current (includes load current) | CLKOUT = 75 MHz, checker board pattern, OS_CLKOUT/DATA = H, CL = 4 pF (see Figure 9) |
VDD = 1.89 V | 97 | 115 | mA | |
IDDIO1 | VDDIO = 1.89 V | 40 | 50 | ||||
VDDIO = 3.6 V | 75 | 85 | |||||
IDDZ | Deserializer supply current power down | PDB = 0 V, All other LVCMOS Inputs = 0 V | VDD = 1.89 V | 100 | 3000 | µA | |
VDDIO = 1.89 V | 6 | 50 | |||||
IDDIOZ | VDDIO = 3.6 V | 12 | 100 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | Input high level | SDA and SCL | 2.2 | VDDIO | V | |
VIL | Input low level voltage | SDA and SCL | GND | 0.8 | V | |
VHY | Input hysteresis | >50 | mV | |||
VOL | Output low level voltage(1) | SDA, IOL = 1.25 mA, VDDIO = 3.3 V | 0 | 0.4 | V | |
Iin | Input current | SDA or SCL, Vin = VDDIO or GND | –15 | 15 | µA | |
Cin | Input capacitance | SDA or SCL | <5 | pF |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
tTCP | Transmit input CLKIN period | 10 MHz to 75 MHz (see Figure 4) | 13.3 | T | 100 | ns |
tTCIH | Transmit input CLKIN high time | 10 MHz to 75 MHz (see Figure 4) | 0.4 × T | 0.5 × T | 0.6 × T | ns |
tTCIL | Transmit input CLKIN low time | 10 MHz to 75 MHz (see Figure 4) | 0.4 × T | 0.5 × T | 0.6 × T | ns |
tCLKT | CLKIN input transition time | 10 MHz to 75 MHz (see Figure 4) | 0.5 | 2.4 | ns | |
SSCIN | CLKIN input | fmod (spread spectrum at 75 MHz) | 35 | kHz | ||
fdev (spread spectrum at 75 MHz) | ±2% |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCL | SCL clock frequency | Standard mode | 100 | kHz | ||
Fast mode | 400 | |||||
tLOW | SCL low period | Standard mode | 4.7 | μs | ||
Fast mode | 1.3 | |||||
tHIGH | SCL high period | Standard mode | 4 | μs | ||
Fast mode | 0.6 | |||||
tHD;STA | Hold time for a start or a repeated start condition (see Figure 18) | Standard mode | 4 | μs | ||
Fast mode | 0.6 | |||||
tSU:STA | Set up time for a start or a repeated start condition (see Figure 18) | Standard mode | 4.7 | μs | ||
Fast mode | 0.6 | |||||
tHD;DAT | Data hold time (see Figure 18) |
Standard mode | 0 | 3.45 | μs | |
Fast mode | 0 | 0.9 | ||||
tSU;DAT | Data set up time (see Figure 18) |
Standard mode | 250 | ns | ||
Fast mode | 100 | |||||
tSU;STO | Set up time for STOP condition (see Figure 18) |
Standard mode | 4 | μs | ||
Fast mode | 0.6 | |||||
tBUF | Bus free time (between STOP and START; see Figure 18) | Standard mode | 4.7 | μs | ||
Fast mode | 1.3 | |||||
tr | SCL and SDA rise time (see Figure 18) |
Standard mode | 1000 | ns | ||
Fast mode | 300 | |||||
tf | SCL and SDA fall time (see Figure 18) |
Standard mode | 300 | ns | ||
Fast mode | 300 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tLHT | Serializer output low-to-high transition time (see Figure 3) | RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 | 200 | ps | ||
RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 | 200 | |||||
tHLT | Serializer output high-to-low transition time (see Figure 3) | RL = 100 Ω, de-emphasis = disabled, VODSEL = 0 | 200 | ps | ||
RL = 100 Ω, de-emphasis = disabled, VODSEL = 1 | 200 | |||||
tDIS | Input data, setup time (see Figure 4) |
DI[23:0], CI1, CI2, CI3 to CLKIN | 2 | ns | ||
tDIH | Input data, hold time (see Figure 4) |
CLKIN to DI[23:0], CI1, CI2, CI3 | 2 | ns | ||
tXZD | Serializer output active to OFF delay (see Figure 6)(1) | 8 | 15 | ns | ||
tPLD | Serializer PLL lock time (see Figure 5)(1)(2)(3) |
RL = 100 Ω | 1.4 | 10 | ms | |
tSD | Serializer delay, latency (see Figure 7)(1) |
RL = 100 Ω | 144 × T | 145 × T | ns | |
tDJIT | Serializer output total jitter (see Figure 8) |
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz | 0.28 | UI(4) | ||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz | 0.27 | |||||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz | 0.35 | |||||
λSTXBW | Serializer jitter transfer (function –3 dB bandwidth) |
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz | 3.3 | MHz | ||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz | 2.3 | |||||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz | 0.8 | |||||
δSTX | Serializer jitter transfer (function peaking) |
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz | 0.86 | dB | ||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz | 0.83 | |||||
RL = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz | 0.28 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tRCP | CLK output period | tRCP = tTCP (CLKOUT) | 13.3 | T | 100 | ns | |
tRDC | CLK output duty cycle | CLKOUT | SSCG = OFF, 10 to 75 MHz | 40% | 50% | 60% | |
SSCG = ON, 10 to 20 MHz | 35% | 59% | 65% | ||||
SSCG = ON, 10 to 65 MHz | 40% | 53% | 60% | ||||
tCLH | LVCMOS low-to-high transition time (see Figure 10) | DO[23:0], CO1, CO2, CO3 | VDDIO = 1.8 V, CL = 4 pF, OS_CLKOUT/DATA = L | 2.1 | ns | ||
VDDIO = 3.3 V, CL = 4 pF, OS_CLKOUT/DATA = H | 2 | ||||||
tCHL | LVCMOS high-to-low transition time (see Figure 10) | DO[23:0], CO1, CO2, CO3 | VDDIO = 1.8 V, CL = 4 pF, OS_CLKOUT/DATA = L | 1.6 | ns | ||
VDDIO = 3.3 V, CL = 4 pF, OS_CLKOUT/DATA = H | 1.5 | ||||||
tROS | Data valid before CLKOUT, setup time (see Figure 14) | VDDIO = 1.71 to 1.89 V or 3 to 3.6 V, CL = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3 | 0.23 × T | 0.5 × T | ns | ||
tROH | Data valid after CLKOUT, hold time (see Figure 14) | VDDIO = 1.71 to 1.89 V or 3 to 3.6 V, CL = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3 | 0.33 × T | 0.5 × T | ns | ||
tDDLT | Deserializer lock time (see Figure 13) |
CLKOUT = 10 MHz, SSC[3:0] = OFF(1) | 3 | ms | |||
CLKOUT = 75 MHz, SSC[3:0] = OFF(1) | 4 | ||||||
CLKOUT = 10 MHz, SSC[3:0] = ON(1) | 30 | ||||||
CLKOUT = 65 MHz, SSC[3:0] = ON(1) | 6 | ||||||
tDD | Deserializer delay, latency (see Figure 11) | CLKOUT = 10 to 75 MHz, SSC[3:0] = OFF(2) | 139 × T | 140 × T | ns | ||
tDPJ | Deserializer period jitter | SSC[3:0] = OFF(3)(2) | CLKOUT = 10 MHz | 500 | 1000 | ps | |
CLKOUT = 65 MHz | 550 | 1250 | |||||
CLKOUT = 75 MHz | 435 | 900 | |||||
tDCCJ | Deserializer cycle-to-cycle jitter | SSC[3:0] = OFF(4)(2)(5) | CLKOUT = 10 MHz | 375 | 900 | ps | |
CLKOUT = 65 MHz | 500 | 1150 | |||||
CLKOUT = 75 MHz | 460 | 1000 | |||||
tIJT | Deserializer input jitter tolerance (see Figure 16) | EQ = OFF, SSCG = OFF, CLKOUT = 75 MHz |
jitter freq < 2 MHz | 0.9 | UI(6) | ||
jitter freq > 6 MHz | 0.5 | ||||||
BIST MODE | |||||||
tPASS | BIST PASS valid time (see Figure 17) |
BISTEN = 1 | 1 | 10 | μs | ||
SSCG MODE | |||||||
fDEV | Spread spectrum clocking deviation frequency | CLKOUT = 10 to 65 MHz, SSC[3:0] = ON | ±0.5% | ±2% | |||
fMOD | Spread spectrum clocking modulation frequency | CLKOUT = 10 to 65 MHz, SSC[3:0] = ON | 8 | 100 | kHz |