SNLS624 September   2018 DSLVDS1048

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Feature
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Probing LVDS Transmission Lines
        2. 9.2.2.2 Threshold
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Decoupling Recommendations
      2. 11.1.2 Differential Traces
      3. 11.1.3 Termination
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)(4)(5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHLD Differential propagation delay high to low CL = 15 pF
VID = 200 mV
(Figure 15 and Figure 16) 		1.2 2 2.7 ns
tPLHD Differential propagation delay low to high 1.2 2 2.7 ns
tSKD1 Differential pulse skew |tPHLD − tPLHD|(3) 0.1 0.4 ns
tSKD2 Differential channel-to-channel skew; same device(4) 0.15 0.5 ns
tSKD3 Differential part-to-part skew(5) 1 ns
tSKD4 Differential part-to-part skew(6) 1.5 ns
tTLH Rise time 0.5 1 ns
tTHL Fall time 0.5 1 ns
tPHZ Disable time high to Z RL = 2 kΩ
CL = 15 pF
(Figure 17 and Figure 18) 		8 14 ns
tPLZ Disable time low to Z 8 14 ns
tPZH Enable time Z to high 9 14 ns
tPZL Enable time Z to low 9 14 ns
fMAX Maximum operating frequency(7) All channels switching 200 250 MHz
(1) All typicals are given for: VCC = 3.3 V, TA = 25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN.
(3) tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel
(4) tSKD2, channel-to-channel skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs.
(5) tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC, and within 5°C of each other within the operating temperature range.
(6) tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max−Min| differential propagation delay.
(7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05-V to 1.35-V peak to peak). Output criteria: 60 / 40% duty cycle, VOL (maximum 0.4 V), VOH (minimum 2.7 V), Load = 15 pF (stray plus probes).