SLVSEE2A February   2018  – April  2018 ESD204

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings -JEDEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Typical Characteristics

ESD204 D001_SLVSEE2.gif
Figure 1. Positive TLP Curve, IO pin to GND (tp = 100 ns)
ESD204 D006_SLVSEE2.gif
Figure 3. Surge Curve (tp = 8/20 µs), any IO pin to GND
ESD204 D004_SLVSEE2.gif
Figure 5. –8-kV IEC 61000-4-2 Clamping Voltage Waveform, GND pin to IO
ESD204 D007_SLVSEE2.gif
Figure 7. Leakage Current vs Temperature, IO pin to GND at 3.6 V Bias
ESD204 D010_SLVSEE2.gif
Figure 9. Capacitance vs Frequency
ESD204 D002_SLVSEE2.gif
Figure 2. Negative TLP Curve, GND to IO pin (tp=100 ns; Plotted as Positive TLP Curve from GND to IO pin)
ESD204 D003_SLVSEE2.gif
Figure 4. 8-kV IEC 61000-4-2 Clamping Voltage Waveform, IO pin to GND
ESD204 D008_SLVSEE2.gif
Figure 6. Capacitance vs Bias Voltage
ESD204 D005_SLVSEE2.gif
Figure 8. DC Voltage Sweep I-V Curve, IO pin to GND
ESD204 D009_SLVSEE2.gif
Figure 10. Differential Insertion Loss