SLVSI66 October   2024 ESD701

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings -JEDEC Specifications
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Application and Implementation
    1. 6.1 Application Information
  8. 7 Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  9. 8 Receiving Notification of Documentation Updates
  10. 9 Support Resources
  11. 10Trademarks
  12. 11Electrostatic Discharge Caution
  13. 12Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA -24 24 V
ILEAK Leakage current at VRWM VIO = ±24 V, I/O to GND 2 10 nA
VBR Breakdown voltage, I/O to GND (1) IIO = ±10 mA 25.5 35.5 V
VHOLD Holding voltage (2) TLP, IO to GND or GND to IO 31
VCLAMP Surge clamping voltage, tp = 8/20 µs (3) IPP = 3 A, I/O to GND 37 V
VCLAMP Surge clamping voltage, tp = 8/20 µs (3) IPP = 3 A, GND to I/O 37 V
VCLAMP TLP clamping voltage, tp = 100 ns (4) IPP = 16 A (100 ns TLP), I/O to GND 41 V
VCLAMP TLP clamping voltage, tp = 100 ns (4) IPP = 16 A (100 ns TLP), GND to I/O 41 V
RDYN Dynamic resistance (5) I/O to GND 0.84 Ω
GND to I/O 0.84
CLINE Line capacitance, IO to GND VIO = 0 V, f = 1 MHz 0.3 0.5 pF
(1) VBR is defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
(3) Device stressed with 8/20 µs exponential decay waveform according to IEC 61000-4-5
(4) Non-repetitive square wave current pulse, Transmission Line Pulse (TLP);  ANSI / ESD STM5.5.1-2008
(5) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A