SPRS742L June 2011 – February 2021 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C
PRODUCTION DATA
The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or the internal OSCCLK (originating from the external crystal or oscillator through the X1/X2 pins). An input mux selects the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL Register (see Figure 8-9). The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the UPLLIMULT and UPLLFMULT fields of the UPLLMULT register. For example, to achieve PLL multiply of 28.5, the integer multiplier should be set to 28, and the fractional multiplier to 0.5. The output clock from the USB PLL must always be 240 MHz. The PLL output clock is then divided by 4—resulting in 60 MHz that the USB needs—before entering a mux that selects between this clock and the PLL input clock (used in the PLL bypass mode). The PLL bypass mode is selected by setting the UPLLIMULT field of the UPLLMULT register to 0. The output clock from the mux becomes the USBPLLCLK (there is not another clock divider). Figure 8-9 shows the USB PLL function and configuration examples. Table 8-23 and Table 8-24 list the integer multiplier configuration values.
SPLLIMULT(5:0) | MULT VALUE |
---|---|
000000 b | Bypass PLL |
000001 b | × 1 |
000010 b | × 2 |
000011 b | × 3 |
000100 b | × 4 |
000101 b | × 5 |
000110 b | × 6 |
000111 b | × 7 |
001000 b | × 8 |
001001 b | × 9 |
001010 b | × 10 |
001011 b | × 11 |
001100 b | × 12 |
001101 b | × 13 |
001110 b | × 14 |
001111 b | × 15 |
010000 b | × 16 |
010001 b | × 17 |
010010 b | × 18 |
010011 b | × 19 |
010100 b | × 20 |
010101 b | × 21 |
010110 b | × 22 |
010111 b | × 23 |
011000 b | × 24 |
011001 b | × 25 |
011010 b | × 26 |
011011 b | × 27 |
011100 b | × 28 |
011101 b | × 29 |
011110 b | × 30 |
011111 b | × 31 |
SPLLIMULT(5:0) | MULT VALUE |
---|---|
100000 b | × 32 |
100001 b | × 33 |
100010 b | × 34 |
100011 b | × 35 |
100100 b | × 36 |
100101 b | × 37 |
100110 b | × 38 |
100111 b | × 39 |
101000 b | × 40 |
101001 b | × 41 |
101010 b | × 42 |
101011 b | × 43 |
101100 b | × 44 |
101101 b | × 45 |
101110 b | × 46 |
101111 b | × 47 |
110000 b | × 48 |
110001 b | × 49 |
110010 b | × 50 |
110011 b | × 51 |
110100 b | × 52 |
110101 b | × 53 |
110110 b | × 54 |
110111 b | × 55 |
111000 b | × 56 |
111001 b | × 57 |
111010 b | × 58 |
111011 b | × 59 |
111100 b | × 60 |
111101 b | × 61 |
111110 b | × 62 |
111111 b | × 63 |